MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1139

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

18.3.10.14 PCI Express Controller Core Clock Ratio Register—0x440
The PCI Express controller core clock ratio register, shown in
of the actual PCI Express controller clock frequency to the default controller core frequency (333 MHz).
This is required only when a PCI Express controller clock other than the default 333 MHz has to be used.
Freescale Semiconductor
Status Code
(Hex)
1C
1D
0E
0F
1A
1B
1E
1F
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Configuration lane number wait (1)
Configuration lane number wait (2)
Configuration lane number wait (3)
Configuration lane number accept
Configuration complete (0)
Configuration complete (1)
Configuration idle (0)
Configuration idle (1)
L0
TX L0; RX L0s entry
TX L0; RX L0s idle
TX L0; RX L0s fast training sequence (FTS)
TX L0s entry (0); RX L0
TX L0s entry (0); RX L0s idle
TX L0s entry (0); RX L0s FTS
TX L0s entry (1); RX L0
TX L0s entry (1); RX L0s idle
TX L0s entry (1); RX L0s FTS
TX L0s idle; RX L0
TX L0s idle; RX L0s entry
TX L0s idle; RX L0s idle
TX L0s idle; RX L0s FTS
TX L0s FTS; RX L0
TX L0s FTS; RX L0s entry
TX L0s FTS; RX L0s idle
LTSSM State Description
Table 18-109. PEX_LTSSM_STAT Status Codes (continued)
Status Code
(Hex)
4C
35
36
37
38
39
3A
3F
7F
49
4A
4B
60
61
62
68
69
6A
6B
75
71
72
73
74
78
Figure
Recovery cfg (0)
Recovery cfg (1)
Recovery idle (0)
Recovery idle (1)
Recovery to configuration
Recovery cfg to configuration
L0 no training
Detect quiet EI
Configuration link width start—RC
Configuration link width accept—RC
Configuration lane number wait—RC
Configuration lane number accept—RC
Loopback slave active (0)
Loopback slave active (1)
Loopback slave exit
Hot reset (0)
Hot reset (1)
Hot reset (0)—RC
Hot reset (1)—RC
Disabled (0)
Disabled (1)
Disabled (2)
Disabled (3)
Disabled (4)
L0 to L1/L2—RC
18-115, is used to program the ratio
LTSSM State Description
PCI Express Interface Controller
18-91