MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 804

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.8
The MIIMADD register is written by the user.
Table 15-46
15.5.3.5.9
MIIMCON, shown in
15-74
19–23
24–26
27–31 Register Address This field represents the 5-bit register address field of Mgmt cycles. Up to 32 registers can be
0–18
Bits
Bits
30
31
Offset eTSEC1:0x2_4528
Reset
Offset eTSEC1:0x2_452C
Reset
W
W
R
R
Scan Cycle Scan cycle. This bit is cleared by default.
Read Cycle Read cycle. This bit is cleared by default but is not self-clearing once set.
PHY Address
0
0
Name
Name
describes the fields of the MIIMADD register.
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MII Management Address Register (MIIMADD)
MII Management Control Register (MIIMCON)
0 Normal operation.
1 The MII management continuously performs read cycles. This is useful for monitoring link fail, for
0 Normal operation.
1 The MII management performs a single read cycle upon the transition of this bit from 0 to 1 using the
example.
PHY address (at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register
Address]). The 0-to-1 transition of this bit also causes the MIIMIND[Busy] bit to be set. The read is
complete when the MIIMIND[Busy] bit clears. Data is returned in register MIIMSTAT[PHY Status].
Figure
Reserved
This field represents the 5-bit PHY address field of Mgmt cycles. Up to 31 PHYs can be addressed
(0 is reserved). Its default value is 0x00.
Reserved
accessed. Its default value is 0x00.
Figure 15-44. MII Mgmt Control Register Definition
Table 15-45. MIIMCOM Descriptions (continued)
15-44, is written by the user.
Figure 15-43. MIIMADD Register Definition
—
Table 15-46. MIIMADD Field Descriptions
—
Figure 15-43
All zeros
All zeros
15 16
Description
Description
shows the MIIMADD register.
18 19
PHY Address
PHY Control
23 24
Freescale Semiconductor
—
26 27
Access: Read/Write
Access: Read/Write
Register
Address
31
31