MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 541

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.5.1
The RNG mode register is used to control the RNG. One operational mode, randomizing, is defined. The
RNG mode register is a writable location but all mode bits are currently reserved. It is documented for the
sake of consistency with the other EU’s. The RNG mode register is shown in
12.4.5.2
The RNG data size register is used to tell the RNG to begin generating random data. The actual contents
of the data size register does not affect the operation of the RNG. After a reset and prior to the first write
of data size, the RNG builds entropy without pushing data onto the FIFO. Once the data size register is
written, the RNG begins pushing data onto the FIFO. Data is pushed onto the FIFO every 256 cycles until
the FIFO is full. The RNG then attempts to keep the FIFO full.
12.4.5.3
This register, shown in
Freescale Semiconductor
Address RNG 0x3_A000
Address RNG 0x3_A018
Address RNG 0x3_A010
Reset
Reset
Reset
W
W
R
W
R
R
0
0
0
RNG Mode Register (RNGMR)
RNG Data Size Register (RNGDSR)
RNG Reset Control Register (RNGRCR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure
12-42, contains three reset options specific to the RNG.
Figure 12-42. RNG Reset Control Register
Figure 12-41. RNG Data Size Register
Figure 12-40. RNG Mode Register
—
All zeros
All zeros
All zeros
—
—
Figure
Security Engine (SEC) 2.1
12-40.
Access: Read/Write
Access: Read/Write
60
Access: Read/Write
RI
61
MI
62
12-63
SR
63
63
63