MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 841

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 15-103
Table 15-106
15.5.3.9.2
The ATTRELI registers are written by the user to specify the extract index and extract length for extracting
received frames. The extract length is typically set to the expected length of extracted packet headers.
Figure 15-104
Freescale Semiconductor
17–18 ELCWT Extracted L2 cache write type. Specifies the write transaction type to perform for the extracted data. For
20–21 BDLWT Buffer descriptor L2 cache write type. specifies the write transaction type to perform for the bufferdescriptor
22–23
26–31
0–16
Bits
19
24
25
Offset eTSEC1:0x2_4BF8; eTSEC3:0x2_6BF8;
Reset
RBDSEN RxBD snoop enable.
W
R
RDSEN Rx data snoop enable.
Name
0
—
—
—
—
describes the fields of the ATTR register.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
describes the definition for the ATTR register.
describes the definition for the ATTRELI register.
Attribute Extract Length and Extract Index Register (ATTRELI)
Reserved
maximum performance, it is recommended that if ELCWT is set to allocate, BDLWT should also be set to
allocate.Writes to cache are always performed with snoop.
00 No allocation performed.
01 Reserved
10 Allocate L2 cache line.
11 Reserved
Reserved
for a receive frame. Writes to cache are always performed with snoop.
00 No allocation performed.
01 Reserved
10 Allocate L2 cache line.
11 Reserved
Reserved
0 Disables snooping of all receive frames data to memory unless ELCWT specifies L2allocation.
1 Enables snooping of all receive frames data to memory.
0 Disables snooping of all receive BD memory accesses unless BDLWT specifies L2 allocation.
1 Enables snooping of all receive BD memory accesses.
Reserved
—
Figure 15-103. ATTR Register Definition
Table 15-106. ATTR Field Descriptions
16
ELCWT
17
18
All zeros
Description
—
19
BDLWT
20
21
22 23
—
Enhanced Three-Speed Ethernet Controllers
RDSEN RBDSEN
24
25
Access: Read/Write
26
—
15-111
31