MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 773

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Offset eTSEC1:0x2_4110; eTSEC3:0x2_6110
Reset
15.5.3.2.4
The TXIC register enables and configures the operational parameters for interrupt coalescing associated
with transmitted frames.
Table 15-18
Freescale Semiconductor
11–15
16–31
3–10
Bits
W
0
1
2
R
ICEN ICCS —
0
Name
ICEN
ICCS Interrupt coalescing timer clock source.
ICFT
ICTT
—
—
describes the fields of the TXIC register.
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Transmit Interrupt Coalescing Register (TXIC)
Interrupt coalescing enable
0 Interrupt coalescing is disabled. Interrupts are raised as they are received.
1 Interrupt coalescing is enabled. If the eTSEC transmit frame interrupt is enabled (IMASK[TXFEN] is set),
0 The coalescing timer advances count every 64 eTSEC Tx interface clocks (TSEC n _GTX_CLK).
1 The coalescing timer advances count every 64 system clocks. This mode is recommended for FIFO
Reserved
Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (TXIC[ICEN] is set), this
value determines how many frames are transmitted before raising an interrupt. The eTSEC threshold counter
is reset to ICFT following an interrupt. The value of ICFT must be greater than zero to avoid unpredictable
behavior.
Reserved
Interrupt coalescing timer threshold. While interrupt coalescing is enabled (TXIC[ICEN] is set), this value
determines the maximum amount of time after transmitting a frame before raising an interrupt. If frames have
been transmitted but the frame count threshold has not been met, an interrupt is raised when the threshold
timer reaches zero. The threshold timer is reset to the value in this field and begins counting down upon
transmission of the first frame having its TxBD[I] bit set. The threshold value is represented in units of 64 clock
periods as specified by the timer clock source (TXIC[ICCS[). The value of ICTT must be greater than zero to
avoid unpredictable behavior.
2
an interrupt is raised when the threshold number of frames is reached (defined by TXIC[ICFT]) or when the
threshold timer expires (determined by TXIC[ICTT]).
operation.
3
Figure 15-14
ICFT
Figure 15-14. TXIC Register Definition
Table 15-18. TXIC Field Descriptions
describes the definition for the TXIC register.
10 11
—
All zeros
Description
15 16
Enhanced Three-Speed Ethernet Controllers
ICTT
Access: Read/Write
15-43
31