MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1071

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
12–15
16–19
8–10
Bits
5–7
11
3
4
Name
WTT
ROE
RTT
NS
TC
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Relaxed ordering enable. This bit when set and the PCI Express device control register[Enable Relaxed] bit
is set will enable the Relaxed Ordering bit for the packet. This bit only applies to memory transactions.
0 Default ordering
1 Relaxed ordering
No snoop enable. This bit when set and the PCI Express device control register[Enable No Snoop] bit is set
will enable the no snoop bit for the packet. This bit only applies to memory transactions.
0 Snoopable
1 No snoop
Reserved
Traffic class. This field indicates the traffic class of the outbound packet. This field only applies to memory
transaction. All other transaction types should set the TC field to 0.
000 TC0
001 TC1
010 TC2
011 TC3
100 TC4
101 TC5
110 TC6
111 TC7
Note: Traffic class settings are passed through to the PCI Express link, but no specific actions are taken in
Reserved
Read transaction type. Read transaction type to run on the PCI Express link
0000 Reserved
0000 Reserved
0010 Configuration read. Supported only when in RC mode and size of less than or equal to 4 bytes and not
0100 Memory read
...
1000 IO read. Supported only when in RC mode and size of less than or equal to 4 bytes and not crossing
...
1111 Reserved
Write transaction type. Write transaction type to run on the PCI Express link.
0000 Reserved
0001 Reserved
0010 Configuration write. Supported only when in RC mode and size of less than or equal to 4 bytes and not
0100 Memory write
0101 Message write. Only support 4-byte size access on a 4-byte address boundary.
...
1000 IO Write. Supported only when in RC mode and size of less than or equal to 4 bytes and not crossing
...
1111 Reserved
the device based on traffic class.
crossing 4-byte address boundary.
Reserved
4-byte address boundary.
Reserved
crossing 4-byte address boundary. Note that inbound write transactions on one PCI express port must
not translate to outbound configuration write transactions on another PCI Express port.
Reserved
4-byte address boundary. Note that inbound write transactions on one PCI express port must not
translate to outbound I/O write transactions on another PCI Express port.
Reserved
Table 18-18. PEXOWAR n Field Descriptions (continued)
Description
PCI Express Interface Controller
18-23