MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 525

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 12-24
Freescale Semiconductor
0–50
Bits Names
51
52
53
54
55
56
57
58
59
60
61
62
63
ERE
DSE
OFE
OFU
KSE
IFE
IFO
ME
AE
—
CE
—
—
IE
describes AFEU interrupt status register fields.
Reserved
Internal error. An internal processing error was detected while performing encryption.
0 No error detected
1 Internal error
Early read error. The AFEU context memory or control was read while the AFEU was performing encryption.
0 No error detected
1 Early read error
Context error. The AFEU mode register, key register, key size register, data size register, or context memory is
modified while AFEU processes data.
0 No error detected
1 Context error
Key size error. A value outside the bounds 1–16 bytes was written to the AFEU key size register
0 No error detected
1 Key size error
Data size error. A value that is not a multiple of 8 bits was written to the AFEU data size register:
0 No error detected
1 Data size error
Mode error. An illegal value was detected in the mode register. Note: writing to reserved bits in mode register is
likely source of error.
0 No error detected
1 Mode error
Address error. An illegal read or write address was detected within the AFEU address space.
0 No error detected
1 Address error
Output FIFO error. The AFEU output FIFO was detected non-empty upon write of AFEU data size register.
0 No error detected
1 Output FIFO non-empty error
Input FIFO error. The AFEU input FIFO was detected non-empty upon generation of done interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Reserved
Input FIFO overflow. The AFEU input FIFO was pushed while full.
1 Input FIFO has overflowed
0 No error detected
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size is
Output FIFO underflow. The AFEU output FIFO was read while empty.
0 No error detected
1 Output FIFO has underflow error
Reserved
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
not a limit to data input. When operated through host-controlled access, the AFEU cannot accept FIFO
inputs larger than 256 bytes without overflowing.
Table 12-24. AFEU Interrupt Status Register Field Descriptions
Description
Security Engine (SEC) 2.1
12-47