MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 604

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DUART
See
When the UIIR is read, the associated DUART serial channel freezes all interrupts and indicates the
highest priority pending interrupt. While this read transaction is occurring, the associated DUART serial
channel records new interrupts, but does not change the contents of UIIR until the read access is complete.
Figure 13-7
Table 13-10
The bits contained in the UIIR registers are described in
13-10
IID[3–0]
IID Bits
0b0001
0b0110
0b0100
Bits
0–1
2–3
5–6
4
7
3. Transmitter holding register empty
4. Modem status
Table 13-11
Offset 0x502
Reset
IID2–1 Interrupt ID bits identify the highest priority interrupt that is pending as indicated in
Name
IID3
IID0
W
FE
Priority
—
Highest Receiver line status Overrun error, parity error, framing error, or
Second
R
Level
shows the bits in the UIIR.
—
0x602
describes the fields of the UIIR.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
FIFOs enabled. Reflects the setting of UFCR[FEN]
Reserved
Interrupt ID bits identify the highest priority interrupt that is pending as indicated in
along with IID2 only when a timeout interrupt is pending for FIFO mode.
IID0 indicates when an interrupt is pending.
0 The UART has an active interrupt ready to be serviced.
1 No interrupt is pending.
for more details.
0
0
Received data
available
Interrupt Type
FE
—
0
1
Figure 13-7. Interrupt ID Registers (UIIR)
Table 13-10. UIIR Field Descriptions
Table 13-11. UIIR IID Bits Summary
break interrupt
Receiver data available or trigger level
reached in FIFO mode
0
2
—
Interrupt Description
0
3
—
Description
Table
IID3
13-11.
0
4
IID2
0
5
Read the line status register.
Read the receiver buffer register or
interrupt is automatically reset if
the number of bytes in the receiver
FIFO drops below the trigger level.
How To Reset Interrupt
Table
Table
Freescale Semiconductor
IID1
0
6
Access: Read only
13-11. IID3 is set
13-11.
—
IID0
1
7