MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1150

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
18.4.1.6
As an initiator, the controller supports both type 0 and type 1 configuration cycles when configured in RC
mode. There are two methods of generating a configuration transaction; refer to
Express Configuration Space Access,”
controller’s internal configuration space, it can be sent out on the PCI Express link, or it can be internally
terminated. The PCI Express TLP header for a type 0 configuration read transaction has
Type[4:0] = 00100 and Fmt[1] = 0; the PCI Express TLP header for a type 0 configuration write
transaction has Type[4:0] = 00100 and Fmt[1] = 1. The PCI Express TLP header for a type 1 configuration
read transaction has Type[4:0] = 00101 and Fmt[1] = 0; the PCI Express TLP header for a type 1
configuration write transaction has Type[4:0] = 00101 and Fmt[1] = 1. Note that all configuration
transactions sent on PCI Express require a response regardless whether they are read or a write
configuration transactions.
The controller does not generate configuration transactions in EP mode. Only inbound configuration
transactions are supported in EP mode.
18.4.1.7
Configuration and I/O writes originating from the PCI Express outbound ATMUs are serialized by the
controller. The logic after issuing a configuration write or IO write will not issue any new transactions until
the outstanding configuration or I/O write is finished. This means that an acknowledgement packet from
the link partner in the form of a CpL TLP packet must be seen or the transaction has timed out. If the CpL
packet contains a CRS status, then the logic will re-issue the configuration write transaction. It will keep
retrying the request until either a status other than CRS is returned or the transaction times out. Note that
configuration writes originating from the PCI Express configuration access registers
(PEX_CONFIG_ADDR/PEX_CONFIG_DATA) are not serialized.
Note that it is possible for outbound configuration read request to be requeued and be placed at the end of
the request queue due to CRS condition.
18.4.1.8
Software message generation is supported in both RC and EP modes.
18.4.1.8.1
Software can choose to send a message by programming PEXOWARn[WTT] = 0x5. A message is sent by
writing a 4-byte transaction in big-endian format that hits in an outbound window configured to send
messages.
18-102
Configuration Space Addressing
Serialization of Configuration and I/O Writes
Messages
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Outbound ATMU Message Generation
for more information. A configuration transaction can hit into the
Section 18.3.7, “PCI
Freescale Semiconductor