MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1163

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

19.4
Table 19-3
In this table and in the register figures and field descriptions, the following access definitions apply:
Freescale Semiconductor
0xE_000C PORDEVSR—POR I/O device status register
0xE_0000 PORPLLSR—POR PLL ratio status register
0xE_0004 PORBMSR—POR boot mode status register
0xE_0008 PORIMPSCR—POR I/O impedance status and control register
0xE_0010 PORDBGMSR—POR debug mode status register
0xE_0014 PORDEVSR2—POR I/O device status register 2
0xE_0020 GPPORCR—General-purpose POR configuration register
0xE_0030 GPIOCR—GPIO control register
CKSTP_OUT
GPOUT[0:7]
Offset
CLK_OUT
•
•
•
•
•
Signal
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Memory Map/Register Definition
summarizes the global utilities registers and their addresses.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O
O
O
Checkstop out
Clock out. Reflects clock signal selected by CLKOCR (see
Register
General-Purpose Output. See
Meaning
Meaning
Timing Assertion—May occur at any time; may be asserted asynchronously to the input clocks.
Timing Assertion/Negation—Depends on the value of CLKOCR[CLK_SEL].
State
State
(CLKOCR)”).
Table 19-2. Detailed Signal Descriptions (continued)
Table 19-3. Global Utilities Block Register Summary
Asserted—Indicates that the e500 core of the MPC8533E is in a checkstop state. The rest of
Negated—Indicates normal operation. After CKSTP_OUT has been asserted, it is negated
Negation—Must remain asserted until the device has been reset with a hard reset.
Asserted—If CLKOCR[ENB] = 1, clock signal selected by CLKOCR[CLK_SEL] is driven.
High impedance—If CLKOCR[ENB] = 0.
the MPC8533E logic remains functional unless.
after the next negation (low-to-high transition) of HRESET.
Register
Signal Multiplexing and GPIO Controls
Power-On Reset Configuration Values
Table 19.4.1.9 on page 19-12
Description
Section 19.4.1.23, “Clock Out Control
Access
Mixed
for details.
R/W
R
R
R
R
R
R
0x nnnn _0000
0x000 n _007F
0x00 nn _ n 0 nn
0x0000_0000
see ref.
see ref.
see ref.
see ref.
Reset
19.4.1.5/19-10
19.4.1.6/19-10
19.4.1.7/19-11
19.4.1.8/19-11
Section/page
19.4.1.1/19-4
19.4.1.2/19-6
19.4.1.3/19-7
19.4.1.4/19-8
Global Utilities
19-3