MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 576

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
Table 12-54
Table 12-55
12-98
Value
Value
0x0C
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1B
0x1E
0x1F
48
49
50
shows the values of crypto-channel states.
shows the bit positions of each potential error. Multiple errors are possible.
DOF. Double fetch FIFO write overflow error.This bit is set when the channel fetch FIFO is full, SOF is set, and
another write has been made to the fetch FIFO. When this bit is set the channel will stop, and an error interrupt
will be activated. The channel will not start again until a continue or reset is given via the CCR register. This bit
can be cleared by writing ‘1’ to this bit in the CPSR Register.
SOF. Single fetch FIFO write overflow Error. This bit is set when the channel fetch FIFO is full and another write
has been made to the fetch FIFO. The channel will set this bit and activate an error interrupt. The channel
continues processing, but the descriptor pointer is lost. The host must clear this bit by writing ‘1’ to this bit in
the CPSR register.
MDTE. A master data transfer error was received from the master bus interface. When the SEC, while acting
as a bus master, detects an error, the controller passes the error to the channel in use. The channel halts and
activates an interrupt. The channel can only be restarted by writing a ‘1’ to the continue or reset bit in the
channel configuration register, or resetting the whole SEC.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-55. Crypto-Channel Pointer Status Register Error Field Descriptions
IDLE
PROCESS_HEADER
FETCH_DESCRIPTOR
CHANNEL_DONE
CHANNEL_DONE_IRQ
CHANNEL_DONE_WRITEBACK
CHANNEL_DONE_NOTIFICATION
CHANNEL_ERROR
REQUEST_PRI_CHA
INC_DATA_PAIR_POINTER
DELAY_DATA_PAIR_UPDATE
EVALUATE_DATA_PAIRS
WRITE_RESET_PRI
RELEASE_PRI_CHA
WRITE_RESET_SEC
RELEASE_SEC_CHA
PROCESS_DATA_PAIRS
WRITE_MODE_PRI
WRITE_MODE_SEC
WRITE_DATASIZE_PRI
DELAY_RNGA_DONE
WRITE_DATASIZE_SEC_SNOOPIN
TRANS_REQUEST_WRITE_SNOOPIN
DELAY_PRI_SEC_DONE
TRANS_REQUEST_WRITE
WRITE_KEY_SIZE
DELAY_PRI_DONE
WRITE_DATASIZE_SEC_SNOOPOUT
TRANS_REQUEST_READ_SNOOPOUT
Channel State
Table 12-54. CHN_STATE Field Values
Error
others
Value
0x2C
0x2D
0x3C
0x20
0x27
0x2A
0x2B
0x2E
0x2F
0x34
0x3A
0x21
0x22
0x23
0x24
0x25
0x26
0x28
0x29
0x30
0x31
0x33
0x35
0x36
0x37
0x38
0x39
DELAY_SEC_DONE
TRANS_REQUEST_READ
EVALUATE_RESET
RESET_WRITE_RESET_PRI
RESET_RELEASE_PRI_CHA
RESET_WRITE_RESET_SEC
RESET_RELEASE_SEC_CHA
RESET_CHANNEL
WRITE_DATASIZE_PRI_POST
RESET_RELEASE_ALL
RESET_RELEASE_ALL_DELAY
REQUEST_SEC_CHA
WRITE_DATASIZE_SEC
WRITE_ICV_SIZE
WRITE_SEC_CHA_GO_SNOOPOUT
WRITE_PRI_CHA_GO_SNOOPIN
WRITE_SEC_CHA_GO_SNOOPIN
DELAY_1CYCLE
TRANS_EXTENT_READ
TRANS_EXTENT3
TRANS_EXTENT4
XOR_WRITE_READ_REG
DELAY_SEC_DONE_TLS
MAC_TO_CIPHER
MAC_TO_CIPHER_DONE
READ_PRI_STATUS
READ_SEC_STATUS
Reserved
Channel State
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