MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 254

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Register Summary
6.12.5.5
6.12.5.6
6-38
Reset
32–34
36–45
46–47
48–51
52–55
SPR 630
Reset
Bits
35
SPR 628
56
57
58
59
60
61
62
63
W
R
W
R
32
32
TLBSELD TLBSEL default value. The default value to be loaded in MAS0[TLBSEL] on a TLB miss exception.
TIDSELD TID default selection value. A 2-bit field that specifies which of the current PID registers should be used
TSIZED
—
Name
X0D
X1D
WD
MD
GD
ED
34
Table 6-32. MAS4 Field Descriptions—Hardware Replacement Assist Configuration
—
—
—
—
ID
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TLBSELD
MAS Register 4 (MAS4)
MAS Register 6 (MAS6)
—
35
Reserved, should be cleared.
0 TLB0
1 TLB1
Reserved, should be cleared.
to load the MAS1[TID] field on a TLB miss exception.
The e500 implementation defines this field as follows:
00 PID0
01 PID1
10 PID2
11 TIDZ (0x00) (all zeros)
Reserved, should be cleared.
Default TSIZE value. Specifies the default value to be loaded into MAS1[TSIZE] on a TLB miss exception.
Reserved, should be cleared.
Default X0 value. Specifies the default value to be loaded into MAS2[X0] on a TLB miss exception.
Default X1 value. Specifies the default value to be loaded into MAS2[X1] on a TLB miss exception.
Default W value. Specifies the default value to be loaded into MAS2[W] on a TLB miss exception.
Default I value. Specifies the default value to be loaded into MAS2[I] on a TLB miss exception.
Default M value. Specifies the default value to be loaded into MAS2[M] on a TLB miss exception.
Default G value. Specifies the default value to be loaded into MAS2[G] on a TLB miss exception.
Default E value. Specifies the default value to be loaded into MAS2[E] on a TLB miss exception.
36
39 40
—
Figure 6-47. MAS Register 4 (MAS4)
Figure 6-48. MAS Register 6 (MAS6)
SPID0
45
TIDSELD
46
47
All zeros
All zeros
47 48
48
Description
—
50 51 52
TSIZED — X0D X1D WD ID MD GD ED
55 56
—
57
Access: Supervisor read/write
Access: Supervisor read/write
58
Freescale Semiconductor
59
60 61
62
62
SAS
63
63