MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1182

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Global Utilities
Table 19-24
19.4.1.22 DDR Clock Disable Register (DDRCLKDR)
Shown in
SDRAM controller.
Table 19-24
19-22
Offset 0xE_0B28
Reset
0–25
W
Bits
R
26
27
28
29
0
13–31
Figure
Bits
2–5
6–9
10
11
12
0
1
describes the bit settings of DDRCDR.
describes the bit settings of DDRCLKDR.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MCK0_DIS
MCK1_DIS
MCK2_DIS
MCK3_DIS
19-22, the DDRCLKDR contains bits that allow disabling the clocks of the DDR
Name
DSO_PZ_OE
DSO_NZ_OE
—
DHC_EN
DSO_EN
DSO_NZ
DSO_PZ
Name
ODT
—
—
Figure 19-22. DDR Clock Disable Register (DDRCLKDR)
Reserved
DDR clock 0 disable
0 MCK0 is enabled.
1 MCK0 is disabled.
DDR clock 1 disable
0 MCK1 is enabled.
1 MCK1 is disabled.
DDR clock 2 disable
0 MCK2 is enabled.
1 MCK2 is disabled.
DDR clock 3 disable
0 MCK3 is enabled.
1 MCK3 is disabled.
Table 19-25. DDRCLKDR Field Descriptions
Table 19-24. DDRCDR Field Descriptions
DDR driver hardware compensation enable
DDR driver software override enable
DDR driver software p-impedance override
DDR driver software n-impedance override
DDR driver software p-impedance OE
DDR driver software n-impedance OE
ODT termination value for IOs
0 ODT termination of 75 ohms
1 ODT termination of 150 ohms
Reserved
25
MCK0_DIS MCK1_DIS MCK2_DIS MCK3_DIS MCK4_DIS MCK5_DIS
26
All zeros
27
Description
Description
28
29
Freescale Semiconductor
Access: Read/Write
30
31