MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 460

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

I
Table 11-6
11-8
2
C Interfaces
.
Bits
0
1
2
3
4
5
6
7
Name
MSTA Master/slave mode START
BCST Broadcast
TXAK Transfer acknowledge. This bit specifies the value driven onto the SDA line during acknowledge cycles for
RSTA Repeated START. Setting this bit always generates a repeated START condition on the bus, provides the
MIEN Module interrupt enable
MEN
MTX
—
describes the bit settings of the I2CCR.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Module enable. This bit controls the software reset of the I
0 The module is reset and disabled. When low, the interface is held in reset but the registers can still be
1 The I
0 Interrupts from the I
1 Interrupts from the I
0 When this bit is changed from one to zero, a STOP condition is generated and the mode changes from
1 Cleared without generating a STOP condition when the master loses arbitration. When this bit is changed
Transmit/receive mode select. This bit selects the direction of the master and slave transfers. When
configured as a slave, this bit should be set by software according to I2CSR[SRW]. In master mode, the bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be
high. The MTX bit is cleared when the master loses arbitration.
0 Receive mode
1 Transmit mode
both master and slave receivers. The value of this bit only applies when the I
receiver, not a transmitter. It also does not apply to address cycles; when the device is addressed as a slave,
an acknowledge is always sent.
0 An acknowledge signal (low value on SDA) is sent out to the bus at the 9th clock after receiving one byte
1 No acknowledge signal response (high value on SDA) is sent.
device with the current bus master. Attempting a repeated START at the wrong time (or if the bus is owned by
another master), results in loss of arbitration. Note that this bit is not readable, which means if a read is
performed to I2CCR[RSTA], a zero value will be returned.
0 No START condition is generated
1 Generates repeated START condition
Reserved
0 Disables the broadcast accept capability
1 Enables the I
accessed.
I
master to slave.
from zero to one, a START condition is generated on the bus, and master mode is selected.
of data.
2
C registers for slave receive or master START can be initialized before setting this bit.
2
C module is enabled. This bit must be set before any other control register bits have any effect. All
2
C to accept broadcast messages at address zero
2
2
Table 11-6. I2CCR Field Descriptions
C module are disabled. This does not clear any pending interrupt conditions.
C module are enabled. An interrupt occurs provided I2CSR[MIF] is also set.
Description
2
C module.
2
C module is configured as a
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