MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 214

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Complex Overview
5.13.1.2
The supervisor mode instruction set defined by the PowerPC architecture is compatible with the e500 with
the following exceptions:
5.13.2
The architecture provides separate instruction and data memory resources. The e500 provides additional
cache control features, including cache locking.
5.13.3
Exception handling is generally the same as that defined in the AIM version of the architecture for the
e500, with the following differences:
An overview of the interrupt and exception handling capabilities of the e500 core can be found in
Section 5.8, “Interrupts and Exception Handling.”
5.13.4
The embedded category defines resources for fixed 4-Kbyte pages and multiple, variable page sizes that
can be configured in a single implementation. TLB management is provided with new instructions and
SPRs.
5.13.5
Embedded category–compliant cores do not share a common reset vector with the AIM version of the
architecture. Instead, at reset fetching begins at address 0xFFFF_FFFC. In addition, the Freescale MMU
category defines specific aspects of the MMU page translation and protection mechanisms. Unlike the
AIM version of the core, as soon as instruction fetching begins, the e500 core is in virtual mode with a
hardware-initialized TLB entry.
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The MMU architecture is different, so some TLB manipulation instructions have different
semantics.
Instructions that support the BATs and segment registers are not implemented.
The critical interrupt provides an extra level of interrupt nesting. The critical interrupt includes
external critical and watchdog timer time-out inputs.
The machine check exception uses the Return from Machine Check Interrupt instruction, rfmci,
and two machine check save/restore registers, MCSRR0 and MCSRR1.
IVPR and IVORs set interrupt vectors individually, but they can be set to the address offsets
defined in the OEA to provide compatibility.
The embedded category does not define a reset vector; execution begins at a fixed virtual address,
0xFFFF_FFFC.
Timer services are generally compatible, although the embedded category defines a new
decrementer auto reload feature, the fixed-interval timer critical interrupt, and the watchdog timer
interrupt, which are implemented in the e500 core.
Memory Subsystem
Exception Handling
Memory Management
Reset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Supervisor Instruction Set
Freescale Semiconductor