MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 416

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
10.3.1.4
The global configuration register (GCR) shown in
allows software to reset the PIC.
Table 10-10
10-20
3–31
Bits Name
19–23
24–31
Offset 0x4_1020
Reset
Bits
0
1
2
W
R
RST Reset. Setting this field forces the PIC to be reset. Cleared automatically when the reset sequence is complete.
—
—
M
RST — M
NCPU Number of CPUs. The number of the highest physical CPU supported. This device implements one CPU (the
Name
0
VID
See
Reserved
Mode. PIC operating mode.
0 Pass-through mode. On-chip PIC is disabled and interrupts detected on IRQ0 are passed directly to the
1 Mixed mode. Interrupts are handled by the normal priority and delivery mechanisms of the PIC. See
Reserved
describes the GCR fields.
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
processor core. See
Section 10.1.4, “Modes of
Global Configuration Register (GCR)
processor core), referenced as P0.
Version ID. Version ID for this interrupt controller. Reports the OpenPIC specification revision level supported
by this implementation. A value of two corresponds to revision 1.2 which is the revision level currently
supported.
Section 10.4.8, “Reset of the
2
3
Figure 10-6. Global Configuration Register (GCR)
Table 10-9. FRR Field Descriptions (continued)
Section 10.1.4, “Modes of
Table 10-10. GCR Field Descriptions
Operation,” for more details.
PIC,” for more information.
Figure 10-6
All zeros
Description
Operation,” for more details.
Description
—
controls the PIC’s operating mode, and
Freescale Semiconductor
Access: Read/Write
31