MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 400

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
The global utilities block monitors two additional interrupt conditions generated by the e500 core
(core_tbint and core_fault_out signals), as shown in
the processor to exit a low-power state. These cases are caused by core conditions, and after the global
utilities logic wakes up the core, they are handled by the core as shown in
10.1.4
Mixed or pass-through mode can be chosen by setting or clearing GCR[M] as described in
Section 10.3.1.4, “Global Configuration Register (GCR).”
10.1.4.1
In mixed mode, the external and internal interrupts are delivered using the normal priority and delivery
mechanisms detailed in
(EIVPR0–EIVPR11),”
(IIDR0–IIDR47).”
10-4
Core Interrupt Type
Unconditional debug
event
Reset
Fixed interval
timer
Decrementer
Machine check
Interrupt Type
Core
Table 10-1. Processor Interrupts Generated Outside the Core—Types and Sources (continued)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(Output from Core)
Modes of Operation
Mixed Mode (GCR[M] = 1)
core_fault_out
Signaled by
core_tbint
(Input to Core)
Table 10-2. e500 Core-Generated Interrupts that Cause a Wake-Up
Signaled by
core_hreset
core_ude
through
Section 10.3.7.1, “External Interrupt Vector/Priority Registers
Section 10.3.7.4, “Internal Interrupt Destination Registers
The source of both of these interrupts is the time base facility within the e500 core. The
integrated logic monitors this core output signal and considers it a processor interrupt for
the purposes of power management (causes the core to exit a low-power state). For more
information about the interaction between core-generated signals and power
management, see
Occurs when the L1 cache has a parity error on a snoop push operation, which can occur
while the core is halted. The integrated logic monitors this signal and considers it a
processor interrupt for the purposes of power management (causes the core to exit a
low-power state).
UDE. Asserting UDE generates an unconditional debug exception type debug interrupt
and sets a bit in the debug status register, DBSR[UDE], as described in
“Debug Status Register (DBSR).”
• HRESET assertion (and negation)
• core_hreset_req . Output from core—caused by writing to the core DBCR0[RST]. This
• core_reset . Output from PIC. See
condition is additionally qualified with MSR[DE] and DBCR0[IDM] bits. Note that
assertion of this signal causes a hard reset of the core only.
core_hreset_req can also be caused by a second timer timeout condition as
described in
(PIR).”
Chapter 19, “Global Utilities.”
Section 10.3.2.6, “Timer Control Register (TCR).”
Table
10-2. Assertion of either of these signals causes
Section 10.3.1.6, “Processor Initialization Register
Sources
Sources
Table
10-2.
Freescale Semiconductor
Section 6.13.2,