MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 279

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
13–15
16–17
Bits
4–8
10
11
12
9
L2INTDIS
L2SRAM
Name
L2DO
L2IO
—
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
L2 data-only. Reserved in full memory-mapped SRAM mode. L2DO may be changed while the L2 is
enabled or disabled.
0 The L2 cache allocates entries for instruction fetches that miss in the L2.
1 The L2 cache allocates entries for processor data loads that miss in the L2 and for processor L1
Note that if L2DO and L2IO are both set, no new lines are allocated into the L2 cache for any processor
transactions, and processor writes and castouts that hit existing data in the cache invalidate those lines
rather than updating them.
L2 instruction-only. Reserved in full memory-mapped SRAM mode. Causes the L2 cache to allocate
lines for instruction cache transactions only. L2IO may be changed while the L2 is enabled or disabled.
0 The L2 cache entries are allocated for data loads that miss in the L2 and for processor L1 castouts.
1 The L2 cache allocates entries for instruction fetch misses, but does not allocate entries for
Note that if L2DO and L2IO are both set, no new lines are allocated into the L2 cache for any processor
transactions, and processor writes and castouts that hit existing data in the cache invalidate those lines
rather than updating them.
Reserved
Cache read intervention disable. Reserved for full memory-mapped SRAM mode. Used to disable
cache read intervention. May be changed while the L2 is enabled or disabled.
0 Cache intervention is enabled. The ECM ensures that if a data read from another device hits in the
1 Cache intervention is disabled
L2 SRAM configuration. Determines the L2 cache/memory-mapped SRAM allocation of the on-chip
memory array. SRAM size depends on the value of L2SIZ. Since L2SIZ is 256 Kbytes, SRAM can have
sizes from 32 Kbytes to 256 Kbytes.
000 No SRAM. Entire array is cache.
001 Entire array is a single SRAM (256-Kbyte SRAM for L2SIZ = 256 Kbytes)
010 One half of the array is an SRAM (128-Kbyte SRAM for L2SIZ = 256 Kbytes)
011 Both halves of the array are SRAMs (two 128-Kbyte SRAMs for L2SIZ = 256 Kbytes)
100 One quarter of the array is an SRAM (one 64-Kbyte SRAM for L2SIZ = 256 Kbytes)
101 Two quarters of the array are SRAMs (two 64-Kbyte SRAMs for L2SIZ = 256 Kbytes)
110 One eighth of the array is an SRAM (one 32-Kbyte SRAM for L2SIZ = 256 Kbytes)
111 Two eighths of the array are SRAMs (two 32-Kbyte SRAMs for L2SIZ = 256 Kbytes)
For one SRAM region L2SRBAR0 is used and for two SRAM regions L2SRBAR0 and L2SRABAR1
are used. Regions of the array that are not allocated to SRAMs will be used as cache memory.
To change these bits, the L2 must be disabled (L2CTL[L2E] = 0).
Note that when setting L2SRAM after cache has been enabled, L2I should be set as well. The fields
can be set simultaneously, and this step is not needed if SRAM size is getting smaller.
Reserved
castouts but does not allocate entries for instruction fetches that miss in the L2. Instruction accesses
that hit in the L2, data accesses, and accesses from the system (including I/O stash writes) are
unaffected.
processor data transactions. Data accesses that hit in the L2, instruction accesses, and accesses
from the system (including I/O stash writes) are unaffected.
L2 cache, it is serviced from the L2 cache.
Table 7-4. L2CTL Field Descriptions (continued)
Description
L2 Look-Aside Cache/SRAM
7-11