MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 800

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.3
The IPGIFG register is written by the user.
Table 15-41
15-70
Offset eTSEC1:0x2_4508; eTSEC3:0x2_6508
Reset 0
16–23
25–31
9–15
Bits
Bits
1–7
30
31
24
0
8
W
R
—
0
Inter-Packet-Gap, Part 1
Inter-Packet-Gap, Part 2
Inter-Packet-Gap, Part 1
1
1
CRC EN
Non-Back-to-Back
Non-Back-to-Back
Duplex
Inter-Packet-Gap
Name
Non-Back-to-Back
describes the fields of the IPGIFG register.
Full
Minimum IFG
0
Back-to-Back
Enforcement
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG)
Name
0
—
—
—
0
CRC enable. If the configuration bit PAD/CRC ENABLE or the per-packet PAD/CRC ENABLE is set,
CRC ENABLE is ignored. This bit is cleared by default.
0 Frames presented to the MAC have a valid length and contain a valid CRC.
1 The MAC appends a CRC on all frames. Clear this bit if frames presented to the MAC have a valid
Full duplex configure. This bit is cleared by default.
0 The MAC operates in half-duplex mode only.
1 The MAC operates in full-duplex mode.
0
length and contain a valid CRC.
0
Table 15-40. MACCFG2 Field Descriptions (continued)
0
7
Reserved
This is a programmable field representing the optional carrier sense window referenced in
IEEE 802.3/4.2.3.2.1 ‘carrier deference’. If carrier is detected during the timing of IPGR1,
the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC
continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x00 to IPGR2. Its default is 0x40 (64d) which
follows the two-thirds/one-third guideline.
Reserved
This is a programmable field representing the non-back-to-back inter-packet-gap in bits. Its
default is 0x60 (96d), which represents the minimum IPG of 96 bits.
This is a programmable field representing the minimum number of bits of IFG to enforce
between frames. A frame is dropped whose IFG is less than that programmed. The default
setting of 0x50 (80d) represents half of the nominal minimum IFG which is 160 bits.
Reserved
This is a programmable field representing the IPG between back-to-back packets. This is
the IPG parameter used exclusively in full-duplex mode and in half-duplex mode if two
transmit packets are sent back-to-back. Set this field to the number of bits of IPG desired.
The default setting of 0x60 (96d) represents the minimum IPG of 96 bits.
—
0
8
Figure 15-38. IPGIFG Register Definition
Table 15-41. IPGIFG Field Descriptions
Inter-Packet-Gap, Part 2
1
9
Non-Back-to-Back
1
0
Figure 15-38
0
0
0
15 16
0
0
describes the definition for IPGIFG.
Description
1
Minimum IFG
Description
Enforcement
0
1
0
0
0
23 24 25
0
—
0
Freescale Semiconductor
1
Inter-Packet-Gap
1
Access: Read/Write
Back-to-Back
0
0
0
0
31
0