MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 469

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

11.4.4.2.1
The input synchronization block synchronizes the input SCL and SDA signals to the system clock and
detects transitions of these signals.
11.4.4.2.2
The SCL and SDA inputs are filtered to eliminate noise. Three consecutive samples of the SCL and SDA
lines are compared to a pre-determined sampling rate. If they are all high, the output of the filter is high.
If they are all low, the output is low. If they are any combination of highs and lows, the output is whatever
the value of the line was in the previous clock cycle.
The sampling rate is equal to a binary value stored in the frequency register I2CDFSRR. The duration of
the sampling cycle is controlled by a down counter. This allows a software write to the frequency register
to control the filtered sampling rate.
11.4.4.3
Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the master
has driven the SCL line low, the slave can drive SCL low for the required period and then release it. If the
slave SCL low period is greater than the master SCL low period, then the resulting SCL bus signal low
period is stretched.
11.4.5
If boot sequencer mode is selected on POR (by the settings on the cfg_boot_seq[0:1] reset configuration
signals, as described in
with one or more EEPROMs through the I
accesses the I
I2CDFR[DFR] field, 0x2C, which corresponds to a divider of 1280. See
Divider Register (I2CFDR),”
to initialize one or more configuration registers of this integrated device.
If the boot sequencer is enabled for normal I
sequence during reset:
Freescale Semiconductor
1. Generate RESET sequence (START then 9 SCL cycles) to the EEPROM twice. This clears any
2. Generate START
3. Transmit 0xA0 which is the 7-bit calling address (0b101_0000) with a write command appended
4. Transmit 0x00 which is the 8-bit starting address
5. Generate a repeated START
6. Transmit 0xA1 which is the 7-bit calling address (0b101_0000) with a read command appended (1
7. Receive 256 bytes of data from the EEPROM (unless the CONT bit is cleared in the data structure).
8. Generate a repeated START
transactions that may have been in progress prior to the reset.
(0 as the least significant bit).
as the least significant bit).
Boot Sequencer Mode
2
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
C1 serial ROM device at the interface frequency designated by the default value of the
Clock Stretching
Input Signal Synchronization
Filtering of SCL and SDA Lines
Section 4.4.3.8, “Boot Sequencer
for additional details of the I2CFDR. The EEPROM(s) can be programmed
2
C interface on IIC1_SCL and IIC1_SDA. The boot sequencer
2
C addressing mode, the I
Configuration”), the I
2
C interface initiates the following
Section 11.3.1.2, “I
2
C1 module communicates
2
C Frequency
I
2
C Interfaces
11-17