MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 339

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
12–15
9–11
Bits
1–3
4–7
8
PRETOACT Precharge-to-activate interval (t
ACTTOPRE Activate to precharge interval (t
ACTTORW Activate to read/write interval for SDRAM (t
CASLAT
Name
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
until an activate or refresh command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
until a precharge command is allowed.
0000 16 clocks
0001 17 clocks
0010 18 clocks
0011 19 clocks
0100 4 clocks
Reserved, should be cleared.
command until a read or write command is allowed.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
MCAS latency from READ command. Number of clock cycles between registration of a READ command
by the SDRAM and the availability of the first output data. If a READ command is registered at clock edge
n
must be programmed at initialization as described in
2
0000 Reserved
0001 1 clock
0010 1.5 clocks
0011 2 clocks
0100 2.5 clocks
0101 3 clocks
0110 3.5 clocks
0111 4 clocks
(DDR_SDRAM_CFG_2).”)
and the latency is
Table 9-10. TIMING_CFG_1 Field Descriptions (continued)
m
clocks, data is available nominally coincident with clock edge
1011 6 clocks
1100 6.5 clocks
1101 7 clocks
1110 7.5 clocks
1111 8 clocks
RAS
0101 5 clocks
0110 6 clocks
0111 7 clocks
…
1111 15 clocks
1000 4.5 clocks
1001 5 clocks
1010 5.5 clocks
RP
). Determines the number of clock cycles from a precharge command
). Determines the number of clock cycles from an activate command
RCD
Description
). Controls the number of clock cycles from an activate
Section 9.4.1.8, “DDR SDRAM Control Configuration
DDR Memory Controller
n
+
m
. This value
9-17