MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1294

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Complete List of Configuration, Control, and Status Registers
B-36
0x5_0800–
0x5_1680–
0x5_07C0
0x5_07D0
0x5_1BF0
0x5_1C00
0x5_1C10
0x5_06E0
0x5_06F0
0x5_0700
0x5_0710
0x5_0720
0x5_0730
0x5_0740
0x5_0750
0x5_0760
0x5_0770
0x5_0780
0x5_0790
0x5_07A0
0x5_07B0
0x5_07E0
0x5_07F0
0x5_15F0
0x5_1600
0x5_1610
0x5_1620
0x5_1630
0x5_1640
0x5_1650
0x5_1660
0x5_1670
Offset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IIVPR39—Internal interrupt 39 vector/priority register
IIDR39—Internal interrupt 39 destination register
IIVPR40—Internal interrupt 40 vector/priority register
IIDR40—Internal interrupt 40 destination register
IIVPR41—Internal interrupt 41 vector/priority register
IIDR41—Internal interrupt 41 destination register
IIVPR42—Internal interrupt 42 vector/priority register
IIDR42—Internal interrupt 42 destination register
IIVPR43—Internal interrupt 43 vector/priority register
IIDR43—Internal interrupt 43 destination register
IIVPR44—Internal interrupt 44 vector/priority register
IIDR44—Internal interrupt 44 destination register
IIVPR45—Internal interrupt 45 vector/priority register
IIDR45—Internal interrupt 45 destination register
IIVPR46—Internal interrupt 46 vector/priority register
IIDR46—Internal interrupt 46 destination register
IIVPR47—Internal interrupt 47 vector/priority register
IIDR47—Internal interrupt 47 destination register
Reserved
MIVPR0—Messaging interrupt 0 (MSG 0) vector/priority
register
MIDR0—Messaging interrupt 0 (MSG 0) destination register
MIVPR1—Messaging interrupt 1 (MSG 1) vector/priority
register
MIDR1—Messaging interrupt 1 (MSG 1) destination register
MIVPR2—Messaging interrupt 2 (MSG 2) vector/priority
register
MIDR2—Messaging interrupt 2 (MSG 2) destination register
MIVPR3—Messaging interrupt 3 (MSG 3) vector/priority
register
MIDR3—Messaging interrupt 3 (MSG 3) destination register
Reserved
MSIVPR0—Message shared interrupt vector/priority register
0
MSIDR0—Message shared interrupt destination register 0
Table B-1. Memory Map (continued)
Register
Access
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
—
—
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8080_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x8000_0000
0x0000_0001
0x1000_0000
0x0000_0001
Reset
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Freescale Semiconductor
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