MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 442

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
Table 10-42
10.3.8.2
There is one CTPR on this device, shown in
Software must write the priority of the current processor task in the CTPR. The PIC uses this value for
comparison with the priority of incoming interrupts. Given several concurrent incoming interrupts, the
highest priority interrupt is asserted to the core if the following apply:
Priority levels from 0 (lowest) to 15 (highest) are supported. Setting the task priority to 15 masks all
interrupts to the processor. Hardware sets the task register to 0x0000_000F during reset or when the Px
field of the processor initialization register is set.
Table 10-48
10-46
28–31
Offset IPIDR0 0x6_0040, IPIDR1 0x6_0050, IPIDR2 0x6_0060, IPIDR3 0x6_0070
0–30
0–27
Reset
Bits
Bits
31
•
•
W
R
The interrupt is not masked
The priority of the interrupt is higher than the values in the CTPR and ISR
(Also accessible at private access offset 0x4_0 xxx ; see
Offset CTPR0 0x6_0080
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0
TASKP Task priority. This field is set from 0 to 15, where 15 corresponds to the highest priority for processor tasks. If
Name
Name
P0
—
—
W
R
describes the IPIDRn fields.
describes the fields of the CTPR.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Processor Current Task Priority Register (CTPR)
Reserved
Processor 0. Determines if processor 0 receives the interrupt. (write only).
0 Processor 0 does not receive the interrupt.
1 Directs the interrupt to processor 0.
Reserved
CTPR[TASKP] = 0xF, no interrupts are signaled to the processor.
Figure 10-43. Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3)
Figure 10-44. Processor Current Task Priority Register (CTPR)
Table 10-47. IPIDR n Field Descriptions
Table 10-48. CTPR Field Descriptions
Figure
—
10-44.
All zeros
—
Section 10.3.8, “Per-CPU
Description
Description
Registers.”)
Access: Read/Write
Freescale Semiconductor
27 28
Access: Write only
TASKP
31
30 31
P0