MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 925

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend
Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),
This enables the external PHY to restart Auto-Negotiations using the configuration set in the AN Advertisement
Set up the MII Mgmt for a write cycle to the external PHY Control register (write the PHY address and Register
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
Write to MII Mgmt Control with 16-bit data intended for the external PHY AN Advertisement register,
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_1x10_0000]
The Control register is at offset address 0x00 from the external PHY address. (in this case 0x11)
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
Write to MII Mgmt Control with 16-bit data intended for the external PHY Control register,
(Uses the PHY address (0x11) and Register address (6) placed in MIIMADD register)
(Uses the PHY address (0x11) and Register address (5) placed in MIIMADD register)
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x2.
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register)
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Table 15-159. RGMII Mode Register Initialization Steps (continued)
Where u must be selected by the user for proper system configuration.
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0110]
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0101]
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_u0uu_uuuu_uuuu_uuuu]
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0001]
Perform an MII Mgmt read cycle of AN Expansion Register.
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
read the MIIMSTAT register and check bit 10. (AN Done)
Check to see if PHY has completed Auto-Negotiation.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
When MIIMIND[BUSY]=0,
When MIIMIND[BUSY]=0,
address),
register.
Ability)
Enhanced Three-Speed Ethernet Controllers
15-195