MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 518

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.4.2.8
The EU go register in the DEU is used to indicate a DES operation may be completed. After the final
message block is written to the input FIFO, the EU go register must be written. The value in the data size
register will be used to determine how many bits of the final message block (always 64) will be processed.
Note that this register has no data size, and during the write operation, the host data bus is not read. Hence,
any data value is accepted. Normally, a write operation with a zero data value is performed. Reading from
this register is not meaningful, but a zero value is always returned, and no error is generated. Writing to
12-40
Bits Name
54
55
56
57
58
59
60
61
62
63
OFU Output FIFO underflow. The DEU output FIFO was read while empty.
OFO Output FIFO overflow. The DEU output FIFO was pushed while full.
KSE
DSE
OFE
IFE
IFU
IFO
ME
AE
Key size error. An inappropriate value (8 being appropriate for single DES, and 16 and 24 being appropriate for
Triple DES) was written to the DEU key size register
0 Key size error enabled
1 Key size error disabled
Data size error (DSE): A value that is not a multiple of 64 bits was written to the DEU data size register.
0 Data size error enabled
1 Data size error disabled
Mode error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
Address error. An illegal read or write address was detected within the DEU address space.
0 Address error enabled
1 Address error disabled
Output FIFO error. The DEU output FIFO was detected non-empty upon write of DEU data size register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
Input FIFO error. The DEU input FIFO was detected non-empty upon generation of done interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Input FIFO underflow. The DEU input FIFO was read while empty.
0 Input FIFO Underflow error enabled
1 Input FIFO Underflow error disabled
Input FIFO overflow. The DEU input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size is not
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
0 Output FIFO overflow error enabled
1 Output FIFO overflow error disabled
DEU EU Go Register (DEUEUG)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-20. DEU Interrupt Control Register Field Descriptions (continued)
a limit to data input. When operated through host-controlled access, the DEU cannot accept FIFO inputs
larger than 256 bytes without overflowing.
Description
Freescale Semiconductor