MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 513

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.2.3
This register, shown in
64. All data to be processed by the DEU must be a multiple of the DES algorithm block size of 64 bits; the
DEU does not automatically pad messages out to 64-bit blocks. If a data size that is not a multiple of 64
bits is written, a data size error will be generated. Only bits 58–63 are checked to determine if there is a
data size error. Since all upper bits are ignored, the entire message length (in bits) can be written to this
register.
This register is cleared when the DEU is reset or re-initialized.
12.4.2.4
This register, shown in
self-clearing bits:
Table 12-17
0–60
Freescale Semiconductor
Offset DEU 0x3_2010
Offset DEU 0x3_2018
Reset
Reset
Bits Names
61
W
W
R
R
0
0
—
RI
describes DEU reset control register fields.
Reserved
Reset interrupt. Writing this bit active high causes DEU interrupts signaling DONE and ERROR to be reset. It
further resets the state of the DEU interrupt status register.
0 Don’t reset
1 Reset interrupt logic
DEU Data Size Register (DEUDSR)
DEU Reset Control Register (DEURCR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure
Table 12-17. DEU Reset Control Register Field Descriptions
Figure
12-15, stores the number of bits in the final message block, which must be
12-16, allows three levels reset of just DEU, as defined by the three
Figure 12-16. DEU Reset Control Register
Figure 12-15. DEU Data Size Register
—
—
All zeros
All zeros
Description
47 48
Security Engine (SEC) 2.1
KEY SIZE
Access: Read/Write
Access: Read/Write
RI MI SR
61 62
12-35
63
63