MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1309

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Index
A
Accumulator (ACC), 6-47
Address maps
Address mask (LBC), 14-12
Address multiplexing (LBC SDRAM), 14-50
Address translation and mapping units (ATMUs)
Addressing
Alignment, byte (PCI/PCI-X), 17-49
Arbitration
Architecture
ASLEEP (global utilities asleep) signal, 19-2, 19-28
ATMUs, see Address translation and mapping units
B
Battery backup, self-refresh mode, 9-72
BBEAR (branch buffer address register), see e500 core,
BBTAR (branch buffer target address register), see e500 core,
Block diagrams
Freescale Semiconductor
addressing on PCI/PCI-X bus, 17-47
inbound windows, 2-9
local access windows, 2-3–2-10
outbound windows, 2-9
PCI bus addressing, 17-48
I
PCI/PCI-X interface, 17-5, 17-42
overview, 1-8
DDR controller, 9-1, 9-41
debug modes, watchpoint monitor, and trace buffer, 21-1
DMA controller, 16-1
DUART, 13-2
e500 coherency module (ECM), 8-1
2
C interface
illegal interactions between inbound ATMUs and local
PCI Express, 18-24
PCI/PCI-X—4 windows, 2-10, 17-19
see also Local access windows
PCI Express, 18-19
PCI/PCI-X—4 windows, 17-16
configuration space, 17-48
I/O space, 17-48
memory space, 17-47
arbitration control, 11-15
loss of arbitration—forcing of slave mode, 11-24
procedure for arbitration, 11-15
registers
registers
endpoint (EP) mode, 18-24
root complex (RC) mode, 18-25
access windows, 2-10
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Index
Boot mode
Boot page translation, 4-7
Boot ROM location (POR), 4-13
Boot sequencer
BUCSR (branch unit control and status register), see e500
Buffer descriptors, see eTSEC, buffer descriptors
Burst operations (PCI)
Bus operations
Byte alignment (PCI/PCI-X), 17-49
C
Chaining
CKSTP_IN (global utilities checkstop in) signal, 19-2
CKSTP_OUT (global utilities checkstop out) signal, 19-3
CLK_OUT (global utilities clock out) signal, 19-3, 19-23
Clocks
eTSEC, 15-2
I
interrupt controller (PIC), 10-47
L2 cache/SRAM, 7-1
local bus controller (LBC), 14-1
PCI Express, 18-2
PCI/PCI-X controller, 17-2
performance monitor, 20-2
security engine (SEC), 12-3
CPU holdoff (POR), 4-15, 8-4
POR status register (PORBMSR), 19-6
boot holdoff mode (POR), 4-16, 8-4
boot page translation, 4-7
I
overview, 1-17, 4-8
POR configuration, 4-16
see PCI/PCI-X controller, bus protocol
PCI/PCI-X, see PCI/PCI-X controller, bus protocol
performance monitor events, 20-27
DDR clock distribution, 9-57
DDR controller clock disable, 19-22
device clock signals summary, 4-3
device clocking operation, 4-21–4-24
eTSEC
2
2
C interface, 11-1
C interface, 11-2, 11-17–11-20
core, registers
see also Signals, clock
CCB (platform) clock, 4-21
Ethernet clocks, 4-23
RapidIO clocks, 4-22
system clock/PCI clock, 4-21
inputs and outputs, 15-9
management clock out (EC_MDC), 15-10, 15-73
minimum CCB frequency equations, 4-22
Index-1
A–C