MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 705

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.5.4.3
This section describes limitations of the local bus SDRAM machine.
14.5.4.3.1
LSDMR[BSMA] is used to multiplex the bank select address. The BSMA field and corresponding
multiplexed address are shown below:
Note that LA12 is the latched value of LAD12.
The highest address signals that the bank selects can be multiplexed with are LA[12:13], which limits the
signals for the row address to LA[14:31]. For a 32-bit port, the maximum width of the local bus, LA[30:31]
are not connected, and the maximum row is LA[14:29]. The local bus SDRAM machine supports 15 rows,
which is sufficient for all devices.
14.5.4.3.2
Page-based interleaving allows bank signals to be multiplexed to the higher-order address signals to leave
room for future upgrades. For example, a user could multiplex the bank select signals to LA[14:15],
leaving LA16 to connect to the address signal for a larger memory size.
This allows the system designer to design one board that can be used with a current generation of SDRAM
devices and upgraded to the next generation without requiring a new board layout.
Freescale Semiconductor
000 LA12–LA13
001 LA13–LA14
…
111 LA19–LA20
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SDRAM Machine Limitations
Analysis of Maximum Row Number Due to Bank Select Multiplexing
Bank Select Signals
Local Bus Controller
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