MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1089

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

transaction from an external source; the source of the captured error is reflected in
PEX_ERR_CAP_STAT[GSID]. Note that after the initial error is captured, no further capturing is
performed until the PEX_ERR_CAP_STAT[ECV] bit is clear.
PEX_ERR_CAP_R3 for the case when the error is caused by an outbound transaction from an internal
source (that is, PEX_ERR_CAP_STAT[GSID] ≠ 0h02), is shown in
Table 18-29
outbound transaction from an internal source.
PEX_ERR_CAP_R3 for the case when the error is caused by an inbound transaction from an external
source (that is, PEX_ERR_CAP_STAT[GSID] = 0h02 for controller 1), is shown in
Table 18-30
inbound transaction from an external source.
Freescale Semiconductor
0–31
Bits
Offset 0xE34
Offset 0xE34
Reset
Reset
0–31
Bits
W
Name
W
R
R
OD2
describes the fields of PEX_ERR_CAP_R3 for the case when the error is caused by an
describes the fields of PEX_ERR_CAP_R3 for the case when the error is caused by an
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
0
Figure 18-34. PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
Figure 18-35. PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
Table 18-33. PCI Express Error Capture Register 3 Field Descriptions
Internal platform header bits 31-0. Contains internal platform header bits 31-0. Note that this field is only
Table 18-34. PEX Error Capture Register 3 Field Descriptions
Name
GH3
valid for outbound internal platform errors. It is not valid for completion time-out errors or
PEX_CONFIG_ADDR/PEX_CONFIG_DATA errors. 0–31Address[1:32]
Internal Source, Outbound Transaction
Internal Source, Outbound Transaction
External Source, Inbound Transaction
External Source, Inbound Transaction
PEX 4th DW (4-byte) header. This field is a don’t care.
All zeros
All zeros
OD2
GH3
Description
Description
Figure
18-34.
PCI Express Interface Controller
Access: Read/Write
Access: Read/Write
Figure
18-31.
31
31
18-41