MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 440

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
Table 10-45
10.3.8
The OpenPIC programming model supports multiprocessor systems of up to 32 separate processors. As
such, the OpenPIC interface specification provides for coordinating both the requesting and servicing of
interrupts among several processor cores within a single integrated device. To fully comply with the
OpenPIC specification, the PIC incorporates several of these multiprocessor capabilities. Because the
value of features such as private address space for per-CPU registers and interprocessor interrupts is fully
realized only in a multi-core environment, their utility in this single-core device is not intuitive.
The registers in
in a multi-core device. The OpenPIC interface specifies that a copy of these registers be available to each
core at the same physical address by using the ID of the processor that initiates the transaction to determine
the set of per-CPU registers to access.
10-44
0–30
Bits Name
31
Offset MIDR0: 0x5_1610, MIDR1: 0x5_1630, MIDR2: 0x5_1650, MIDR3: 0x5_1670
Reset 0
P0
—
W
R
Reserved
Processor 0. Indicates that processor 0 handles any interrupt. This bit is meaningful only in a multi-core device.
Because this is a single-core device, all interrupts that are serviced internally are always directed to processor 0.
Permanently set and read only.
1 Interrupt directed to processor 0.
describes the MIDR fields.
0
Per-CPU Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 10-46
0
1
Table 10-46. Per-CPU Registers—Private Access Address Offsets
Figure 10-41. Messaging Interrupt Destination Registers (MIDRs)
0
2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IPI 0 dispatch register (IPIDR0)
IPI 1 dispatch register (IPIDR1)
IPI 2 dispatch register (IPIDR2)
IPI 3 dispatch register (IPIDR3)
Current task priority register (CTPR)
Who am I register (WHOAMI0)
Interrupt acknowledge register (IACK)
End of interrupt register (EOI)
are called per-CPU registers, because they would be duplicated for each core
Table 10-45. MIDR n Field Descriptions
Register Name
Description
—
0x4_00A0
0x4_0040
0x4_0050
0x4_0060
0x4_0070
0x4_0080
0x4_0090
0x4_00B0
Offset
Freescale Semiconductor
Access: Mixed
30 31
P0
1