MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 868

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
The possible port mode combinations supported across both eTSECs are shown in
The following restrictions apply in any of the FIFO modes:
No Ethernet-specific features (such as MAC address matching) or layer 2 properties (such as Ethertype)
are available in FIFO mode.
15.6.2.1
In the encoded (non GMII-style) FIFO modes, link-level flow control is provided to the eTSEC transmitter
on the COL signal of the controlling eTSEC, while back pressure to the remote transmitter is sent on the
CRS signal (which acts as an output signal only in FIFO mode). Owing to the synchronization delay of
responding to flow control on signal COL, the eTSEC cannot stop transmission immediately, but may
require up to 8 clock cycles before transmission is paused. The eTSEC will issue flow control either when
software forces it (via the FIFOCFG[FFC] bit), or when the Rx FIFO reaches its high watermark.
15.6.2.2
If FIFOCFG[CRCAPP] is enabled, the FIFO interface will automatically append a 4-byte CRC to each
transmitted packet. Alternatively, if FIFOCFG[CRCAPP] is cleared, TxBD[TC] provides a per-packet
override to append CRC. The IEEE 802.3 standard CRC-32 algorithm is used, where the least significant
bit of each byte (TXD[0]) is combined into the CRC ahead of the most significant bit (TXD[]).
Accordingly, the CRC result, CRC[31:0] is transmitted onto the interface in bit-reversed order,
CRC[24:31], CRC[16:23], CRC[8:15], CRC[0:7].
Automatic checking of CRC-32 checksums received over the FIFO interface is enabled by setting
FIFOCFG[CRCCHK]. CRC errors are recorded in the RxBD[CR] flag of every last buffer. Like transmit,
the receiver combines data into the CRC in the order least significant data bit (RXD[0]) to most significant
bit (RXD[]). The last 4 bytes of the packet are assumed to be CRC whenever FIFOCFG[CRCCHK] is
enabled, and these bytes are returned as part of the data buffer.
15-138
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Transferred packets must be a minimum of 10 bytes, and no more than 9600 bytes in length.
Although TCP/IP offload is supported, the receive queue filer table must be limited to as many
entries as eTSEC can search every packet. See
how to determine maximum table size for an application.
eTSEC requires received packets to have a minimum inter-packet gap of three cycles.
On transmission, the minimum inter-packet gap is three cycles if CRC is not automatically
appended; each CRC data beat reduces this minimum inter-packet gap down to no less than one
cycle.
Flow Control
CRC Appending and Checking
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 15-127. Port Mode Combinations Supported by eTSECs
8-bit FIFO & Ethernet,
8-bit FIFO Only
Mode Option
Ethernet only
mixed
Reduced Ethernets
8-bit FIFO port 1 or
eTSEC1 Signals
8-bit FIFO port 1
All Ethernets
Section 15.6.5.1.1, “Filing Rules,”
8-bit FIFO port 2 or
Reduced Ethernets
eTSEC3 Signals
8-bit FIFO port 2
All Ethernets
Table
Freescale Semiconductor
15-127.
for guidance on