MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 546

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
Table 12-38
1
12-68
The following bits are described for information only. They are not under direct user control.
51–53 SCM Sub-cipher-mode. Specifies additional options specific to particular cipher modes.
54–55
The following bits are controlled through the MODE0 field of the descriptor header.
56–57 ECM Extend cipher mode. Used in combination with bits 61–62 (cipher mode) to define the mode of AES operation.
61–62
0–50
Bits
SRT is not a new AES mode, it is an AESU method of performing AES-CTR mode with reduced context loading overhead
58
59
60
63
specifically for performing SRTP. It should be used with descriptor type 0010_0 srtp. See
Mode,” for more information on how SRT mode reduces context loading overhead.
Name
RDK Restore decrypt key (RDK). Specifies that key data write will contain pre-expanded key (decrypt mode only). See
CM
FM
IM
ED
—
—
describes the AESU mode register fields.
Reserved
Reserved, must be set to zero.
See
Final MAC (FM). Processes final message block and generates final MAC tag at end of message processing
(CCM mode only)
0 Do not generate final MAC tag
1 Generate final MAC tag after CCM processing is complete.
Initialize MAC(IM). Initializes AESU for new message (CCM mode only)
0 Do not initialize (context will be loaded by host)
1 Initialize new message with nonce
note below on use of RDK bit.
0 Expand the user key prior to decrypting the first block
1 Do not expand the key. The expanded decryption key will be written following the context switch.
Cipher mode. Used in combination with bits 56–57 (extend cipher mode) to define the mode of AES operation.
See
Encrypt/decrypt. If set, AESU operates the encryption algorithm; if not set, AESU operates the decryption
algorithm.
0 Perform decryption
1 Perform encryption
Note: This bit is ignored if CM is set to 0b11—CTR mode.
• XOR cipher mode: specifies the number of sources to be XORed together. Valid values are 2 and 3.
• For all other cipher modes, this field must be 0.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-39
Table 12-39
CCM (without ICV comparison)
for mode bit combinations.
for mode bit combinations.
CCM with ICV comparison
Reserved
Table 12-38. AESU Mode Register
Table 12-39. AES Cipher Modes
Mode
SRT
CBC
XOR
ECB
CTR
1
Description
ECM (56–57)
00
00
00
01
10
11
11
all others
CM (61–62)
00
01
11
11
00
00
11
Section 12.4.6.9.3, “Context for SRT
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