MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 46

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure
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xlvi
Integer Exception Register (XER) .......................................................................................... 6-8
Condition Register (CR) ......................................................................................................... 6-9
Link Register (LR) ................................................................................................................ 6-11
Count Register (CTR) ........................................................................................................... 6-11
Machine State Register (MSR) ............................................................................................. 6-11
Processor ID Register (PIR).................................................................................................. 6-13
Processor Version Register (PVR) ........................................................................................ 6-13
System Version Register (SVR)............................................................................................ 6-14
Timer Control Register (TCR) .............................................................................................. 6-14
Timer Status Register (TSR) ................................................................................................. 6-15
Time Base Upper/Lower Registers (TBU/TBL)................................................................... 6-16
Decrementer Register (DEC) ................................................................................................ 6-16
Decrementer Auto-Reload Register (DECAR)..................................................................... 6-17
Save/Restore Register 0 (SRR0) ........................................................................................... 6-17
Save/Restore Register 1 (SRR1) ........................................................................................... 6-17
Critical Save/Restore Register 0 (CSRR0) ........................................................................... 6-17
Critical Save/Restore Register 1 (CSRR1) ........................................................................... 6-18
Data Exception Address Register (DEAR) ........................................................................... 6-18
Interrupt Vector Prefix Register (IVPR) ............................................................................... 6-18
Interrupt Vector Offset Registers (IVORn) ........................................................................... 6-18
Exception Syndrome Register (ESR).................................................................................... 6-19
Machine Check Save/Restore Register 0 (MCSRR0)........................................................... 6-20
Machine Check Save/Restore Register 1 (MCSRR1)........................................................... 6-20
Machine Check Address Register (MCAR).......................................................................... 6-21
Machine Check Address Register Upper (MCARU)............................................................ 6-21
Machine Check Syndrome Register (MCSR) ....................................................................... 6-21
Software-Use SPRs (SPRG0–SPRG7 and USPRG0)........................................................... 6-22
Branch Buffer Entry Address Register (BBEAR) ................................................................ 6-23
Branch Buffer Target Address Register (BBTAR)................................................................ 6-23
Branch Unit Control and Status Register (BUCSR) ............................................................. 6-24
Hardware Implementation-Dependent Register 0 (HID0).................................................... 6-25
Hardware Implementation-Dependent Register 1 (HID1).................................................... 6-26
L1 Cache Control and Status Register 0 (L1CSR0).............................................................. 6-28
L1 Cache Control and Status Register 1 (L1CSR1).............................................................. 6-29
L1 Cache Configuration Register 0 (L1CFG0)..................................................................... 6-30
L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 6-31
Process ID Registers (PID0–PID2)....................................................................................... 6-32
MMU Control and Status Register 0 (MMUCSR0) ............................................................. 6-32
MMU Configuration Register (MMUCFG) ......................................................................... 6-32
TLB Configuration Register 0 (TLB0CFG) ......................................................................... 6-33
TLB Configuration Register 1 (TLB1CFG) ......................................................................... 6-34
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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