MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 349

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 9-16
Freescale Semiconductor
Bits
2–3
5–7
0
1
4
8
9
SET_REF Set refresh. Forces an immediate refresh to be issued to the chip select specified by
SET_PRE Set precharge. Forces a precharge or precharge all to be issued to the chip select specified by
MD_SEL
CS_SEL
MD_EN
Name
—
—
describes the DDR_SDRAM_MD_CNTL fields.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Note that MD_EN, SET_REF, and SET_PRE are mutually exclusive; only
one of these fields can be set at a time.
Mode enable. Setting this bit specifies that valid data in MD_VALUE is ready to be written to DRAM as one
of the following commands:
The specific command to be executed is selected by setting MD_SEL. In addition, the chip select must be
chosen by setting CS_SEL.MD_EN is set by software and cleared by hardware once the command has
been issued.
0 Indicates that no mode register set command needs to be issued.
1 Indicates that valid data contained in the register is ready to be issued as a mode register set command.
Reserved
Select chip select. Specifies the chip select that will be driven active due to any command forced by
software in DDR_SDRAM_MD_CNTL.
00 Chip select 0 is active
01 Chip select 1 is active
10 Chip select 2 is active
11 Chip select 3 is active
Reserved
Mode register select. MD_SEL specifies one of the following:
Note that MD_SEL contains the value that will be presented onto the memory bank address pins (MBA n )
of the DDR controller.
000 MR
001 EMR
010 EMR2
011 EMR3
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit will be set by software and cleared by hardware once the
command has been issued.
0 Indicates that no refresh command needs to be issued.
1 Indicates that a refresh command is ready to be issued.
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit will be set by software and cleared by hardware once the
command has been issued.
0 Indicates that no precharge all command needs to be issued.
1 Indicates that a precharge all command is ready to be issued.
• MODE REGISTER SET
• EXTENDED MODE REGISTER SET
• EXTENDED MODE REGISTER SET 2
• EXTENDED MODE REGISTER SET 3
• During a mode select command, selects the SDRAM mode register to be changed
• During a precharge command, selects the SDRAM logical bank to be precharged. A precharge all
• During a refresh command, this field is ignored.
command ignores this field.
Table 9-16. DDR_SDRAM_MD_CNTL Field Descriptions
NOTE
Description
DDR Memory Controller
9-27