MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1108

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
Table 18-58
18.3.8.3.8
The PCI Express secondary status register is shown in
may be masked by corresponding bits in the secondary status interrupt mask register
(PEX_SS_INTR_MASK) and that by default all of the errors are masked. See
“Secondary Status Interrupt Mask Register (RC-Mode
Table 18-61
18-60
Offset 0x1E
Reset
W w1c
R DPE
15
10–9
Bits
Bits
7–4
3–0
7–0
15
14
13
12
11
8
describes the I/O limit register fields.
describes the PCI Express secondary status register fields.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SSE
PCI Express Secondary Status Register—0x1E
w1c
14
Address Decode Type Specifies the number of I/O address bits.
Table 18-61. PCI Express Secondary Status Register Field Description
I/O Limit Address
RMA
w1c
13
Table 18-60. PCI Express I/O Limit Register Field Description
MDPE
Name
Name
RMA
DPE
SSE
RTA
STA
—
—
Figure 18-65. PCI Express Secondary Status Register
RTA
w1c
12
STA
w1c
11
Specifies bits 15:12 of the I/O space ending address
0x00 16-bit I/O address decode
0x01 32-bit I/O address decode
All other settings reserved.
Detected parity error. This bit is set whenever the secondary side
receives a poisoned TLP regardless of the state of the parity error
response bit.
Signaled system error. This bit is set when a device sends a ERR_FATAL
or ERR_NONFATAL message, provided the SERR enable bit in the
command register is set to enable reporting.
Received master abort. This bit is set when the secondary side receives
an unsupported request (UR) completion.
Received target abort. This bit is set when the secondary side receives
a completer abort (CA) completion.
Signaled target abort. This bit is set when the secondary side issues a
CA completion.
Reserved
Master data parity error. This bit is set when the parity error response bit
is set and the secondary side requestor receives a poisoned completion
or poisons a write request. If the parity error response bit is cleared, this
bit is never set.
Reserved
10
—
9
MDPE
w1c
All zeros
8
Figure
Only)—0x5A0” for more information.
7
18-65. Note that the errors in this register
Description
Description
Section 18.3.10.20,
—
Freescale Semiconductor
Access: Mixed
0