MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 176

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Reset, Clocking, and Initialization
4.4.3.12
The eTSEC1 protocol inputs, shown in
the eTSEC1 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in
Status Register (PORDEVSR).”
4.4.3.13
The eTSEC3 protocol inputs, shown in
the eTSEC3 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in
Status Register (PORDEVSR).”
4-18
TSEC1_TXD[0:1]
TSEC3_TX_ER
Default (11)
Functional
Functional
Default (1)
Signal
Signal
eTSEC1 Protocol
eTSEC3 Protocol
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
Reset Configuration
cfg_tsec1_prtcl[0:1]
cfg_tsec3_reduce
Name
Name
Table 4-19. eTSEC3/eTSEC4 Width Configuration
Table 4-20. eTSEC1 Protocol Configuration
(Binary)
(Binary)
Value
Value
00
01
10
11
0
1
Table
Table
The eTSEC1 controller operates using 8-bit FIFO protocol.
The eTSEC1 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in
Width”).
The eTSEC1 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in
Width”).
The eTSEC1 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in
Width”) (default).
eTSEC3 Ethernet interface operates in reduced mode, either RTBI, RGMII
or RMII, or 8-bit FIFO mode.
eTSEC3 Ethernet interface operates in standard TBI, GMII, MII, or 8-bit
FIFO mode.
(default).
4-20, select the protocol (FIFO, MII, GMII or TBI) used by
4-21, select the protocol (FIFO, MII, GMII or TBI) used by
Meaning
Meaning
Section 19.4.1.4, “POR Device
Section 19.4.1.4, “POR Device
Section 4.4.3.10, “eTSEC1
Section 4.4.3.10, “eTSEC1
Section 4.4.3.10, “eTSEC1
Freescale Semiconductor