MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 423

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

16–21
Table 10-21
Freescale Semiconductor
8–14
Bits Name
0–4
5–7
15
(41.625 x 106 ticks/sec) × (60 sec/min) × (60 min/hr) = total ticks/hr generating 1 interrupt/hr
Offset 0x4_1300
Reset
1
W
R
System Clock
Counting down from 59 through 0 requires 60 ticks.
ROVR Roll-over control for cascaded timers only. Specifies behavior when count reaches zero by identifying the source
RTM Real time mode. Specifies the clock source for the PIC timers.
—
—
—
333 MHz
0
Reserved
of the reload value. Cascaded timers are always reloaded with their base count value when the more significant
timer in the cascade (the upstream timer) is zero. Bits 5–7 correspond to timers 2–0. Note that global timer 3
always reloads with its base count register.
0 Timer does not roll over. When the count reaches zero, current count register is reloaded with the base count
1 Timer rolls over at zero to all ones. (When the count reaches zero, current count register is reloaded with
000 All timers reload with base count.
001 Timers 1 and 2 reload with base count, timer 0 rolls over (reloads with 0xFFFF_FFFF).
010 Timers 0 and 2 reload with base count, timer 1 rolls over (reloads with 0xFFFF_FFFF).
011 Timer 2 reloads with base count, timers 0 and 1 roll over (reload with 0xFFFF_FFFF).
100 Timers 0 and 1 reload with base count, timer 2 rolls over (reloads with 0xFFFF_FFFF).
101 Timer 1 reloads with base count, timers 0 and 2 roll over (reload with 0xFFFF_FFFF).
110 Timer 0 reloads with base count, timers 1 and 2 roll over (reload with 0xFFFF_FFFF).
111 Timers 0, 1, and 2 roll over (reload with 0xFFFF_FFFF).
Reserved
0 Timer clock frequency is a ratio of the frequency of the platform (CCB) clock as determined by the CLKR field.
1 The RTC signal is used to clock the PIC timers. If this bit is set, the CLKR field has no meaning.
Reserved
describes the TCR fields.
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
register value.
0xFFFF_FFFF.)
This is the default value.
Table 10-20. Parameters for Hourly Interrupt Timer Cascade Example
4
Clock Ratio
5
ROVR
Figure 10-16. Example Calculation for Cascaded Timers
1 / 8
7
Figure 10-17. Timer Control Register (TCR)
8
Table 10-21. TCR Field Descriptions
Timer Clock
41.625 MHz
—
14
All zeros
RTM
Description
15
(0x027B_25A8)
Timer 0 Count
41.625 x 10
16
—
6
Timer 1 Count
(0x0000_0036)
21 22 23 24
CLKR
59
1
Programmable Interrupt Controller
Timer 2 Count
(0x0000_0036)
—
Access: Read/Write
59
28 29
CASC
10-27
31