MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1325

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Index
Freescale Semiconductor
PCI/PCI-X
performance monitor, descriptions, 20-3
PIC, 10-17
processor version register (PVR), 19-18
security engine (SEC)
configuration header registers, 17-30–17-42, 17-59
memory-mapped registers
global registers, 10-17–10-22
global timer registers, 10-22–10-27
interrupt source configuration registers, 10-22–10-25,
message registers, 10-33–10-35
non-accessible registers
per-CPU registers, 10-43–10-47
performance monitor mask registers, 10-31–10-33
summary registers, 10-27–10-31
AESU, 12-67–12-79
configuration access registers, 18-9–18-12,
error management registers, 18-29–18-42
IP block revision registers, 18-18–18-19
pwr mgmt and message registers, 18-13–18-18
32-bit memory base address register, 17-37
64-bit high memory base address register, 17-38
64-bit low memory base address register, 17-37
arbiter configuration register (PBACR), 17-42
base address registers, 17-36–17-38
base class code register, 17-35
bus function register (PBFR), 17-41
bus status register, 17-32, 17-49, 17-53, 17-65, 17-66
cache line size register, 17-35
capabilities pointer register, 17-39
command register, 17-31, 17-59
configuration and status register base address
device ID register, 17-31, 17-39
interrupt line register, 17-39
interrupt pin register, 17-40
latency timer register, 17-36
maximum grant (MAX GNT) register, 17-40
maximum latency (MAX LAT) register, 17-41
programming interface register, 17-34
revision ID register, 17-34
subclass code register, 17-35
vendor ID, 17-30, 17-38
ATMU inbound registers, 17-19–17-23
ATMU outbound registers, 17-16–17-19
configuration access registers, 17-14–17-15, 17-60
error management registers, 17-23–17-29
in-service register (ISR), 10-49
interrupt pending register (IPR), 10-47
interrupt request register (IRR), 10-47
10-38–10-43
18-42–18-43
(PCSRBAR), 17-36
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset
RMON support, see eTSEC, modes of operation
RTC (real time clock) signal, 4-3, 4-23, 10-25, 10-26, 19-29
RTS, see DUART_RTS[0:1]
S
SCL (I
SD_RX[7:0]/SD_RX[7:0] (PCI Express serial data input and
SD_TX[7:0]/SD_TX[7:0] (PCI Express serial data output
SDA (I
SDRAM interface (LBC), 14-47–14-58
Security engine (SEC)
system version register (SVR), 19-19
trace buffer, 21-16–21-23
trigger out source register, 21-24
watchpoint monitor, 21-10–21-16
core reset through PIC register, 10-20
hard reset actions, 4-8
HRESET_REQ control, 19-20
operations, 4-8
power-on reset (POR)
requests from RapidIO and PCI Express, 19-18
SEC, channel reset, 12-103
signals summary, 4-2
soft request, 19-18
soft reset actions, 4-8
<italics>see also Local bus controller (LBC), SDRAM
advanced encryption standard execution unit (AESU),
AFEU, 12-42–12-50
controller registers, 12-109–12-115
crypto-channel, 12-92–12-102
DEU, 12-33–12-41
interrupt registers, 12-110–12-112
KEU, 12-80–12-91
MDEU, 12-50–12-62
PKEU, 12-26–12-32
RNG, 12-63–12-67
configuration, see Power-on reset (POR), configuration
sequence of events, 4-9
see also Signals, reset
and reconfiguring the eTSEC, 15-142
complement) signals, 18-5
and complement) signals, 18-5
contexts
restore decrypt key (RDK) operation, 12-69
Rinjdael algorithm, 12-7
2
interface
12-7, 12-67
CBC mode, 12-76
CCM mode, 12-77
counter mode, 12-76
SRT mode, 12-76
2
C serial clock) signal, 11-3, 11-4
C serial data) signal, 11-3, 11-4
Index-17
S–S