MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 871

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.6.3
This section describes the operation of the eTSEC. First, the software initialization sequence is described.
Next, the software (Ethernet driver) interface for transmitting and receiving frames is reviewed. Frame
filtering and receive filing algorithm features are also discussed. The section concludes with interrupt
handling, inter-packet gap time, and loop back descriptions.
15.6.3.1
This sections describes which registers are reset due to a hard or software reset and what registers the user
must initialize prior to enabling the eTSEC.
15.6.3.1.1
A hard reset occurs when the system powers up. All eTSEC’s registers and control logic are reset to their
default states after a hard reset has occurred. In this state, each eTSEC behaves like a PowerQUICC III
device, except for the absence of out-of-sequence TxBD features. That is, initially TCP/IP off-load is
disabled and only single RxBD and TxBD rings are accessible.
15.6.3.1.2
After the system has undergone a hard reset, software must initialize certain basic eTSEC registers. Other
registers can also be initialized during this time, but they are optional and must be determined based on the
requirements of the system. See
for register initialization.
After the initialization of registers is performed, the user must execute the following steps in the order
described below to bring the eTSEC into a functional state (out of reset):
Freescale Semiconductor
1. Write to the MACCFG1 register and set the appropriate bits. These need to include RX_EN and
TX_EN. To enable flow control, Rx_Flow and Tx_Flow should also be set.
Gigabit Ethernet Controller Channel Operation
Initialization Sequence
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Hardware Controlled Initialization
User Initialization
Table 15-130. Steps for Minimum Register Initialization
1. Set and clear MACCFG1 [Soft_Reset]
2. Initialize MACCFG2
3. Initialize MAC station address
4. Set up the PHY using the MII Mgmt Interface
5. Configure the TBI control to TBI or GMII
6. Clear IEVENT
7. Initialize IMASK
8. Initialize RCTRL
9. Initialize DMACTRL
Table 15-3
for the register list.
Description
Table 15-130
Enhanced Three-Speed Ethernet Controllers
describes the minimum steps
15-141