MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 511

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.4.1.10.1 PKEU Parameter Memory A
This 2048 bit memory is used typically as an input parameter memory space. For modular arithmetic
routines, this memory operates as one of the operands of the desired function. For elliptic curve routines,
this memory is segmented into four 512 bit memories, and it is used to specify particular curve parameters
and input values.
12.4.1.10.2 PKEU Parameter Memory B
This 2048 bit memory is used typically as an input parameter memory space, as well as the result memory
space. For modular arithmetic routines, this memory operates as one of the operands of the desired
function, as well as the result memory space. For elliptic curve routines, this memory is segmented in to
four 512 bit memories, and it is used to specify particular curve parameters and input values, as well as to
store result values.
12.4.1.10.3 PKEU Parameter Memory E
This 2048 bit memory is non-segmentable, and stores the exponent for modular exponentiation, or the
multiplier k for elliptic curve point multiplication. This memory space is write only; a read of this memory
space causes an address error to be reflected in the PKEU interrupt status register.
12.4.1.10.4 PKEU Parameter Memory N
This 2048 bit memory is non-segmentable, and stores the modulus for modular arithmetic and F
elliptic
p
curve routines. For F
m elliptic curve routines, this memory stores the irreducible polynomial.
2
12.4.2
Data Encryption Standard Execution Unit (DEU)
This section contains details about the data encryption standard execution unit (DEU), including modes of
operation, status and control registers, and FIFOs.
Most of the registers described here are not normally accessed by the host. They are documented here
mainly for debug purposes. In typical operation, the DEU is used through channel-controlled access,
which means that most reads and writes of DEU registers are directed by the SEC channels. Driver
software performs host-controlled register accesses on only a few registers for initial configuration and
error handling.
12.4.2.1
DEU Mode Register (DEUMR)
The DEUMR mode register contains 3 bits which are used to program DEU operation.
The mode register is cleared when the DEU is reset or re-initialized. Setting a reserved mode bit generates
a data error. If the mode register is modified during processing, a context error is generated.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
12-33