MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 741

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
TSEC n _RXD[7:0]
TSEC n _TX_CLK
TSEC n _RX_ER
Signal
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 15-2. eTSEC Signals—Detailed Signal Descriptions (continued)
I/O
I
I
I
Receive data in. In GMII mode, TSEC n _RXD[7:4] with TSEC n _RXD[3:0], represent one complete
octet of data to be transferred from the PHY to the MAC when TSEC n _RX_DV is asserted.
In TBI mode, TSEC n _RXD[7:4] represents RCG[7:4]. Together, with RCG[9:8] and RCG[3:0],
they represent the 10-bit encoded symbol of GMII receive signals.
In GMII or MII mode, TSEC n _RXD[3:0] represents a nibble of data to be transferred from the PHY
to the MAC when TSEC n _RX_DV is asserted. A completely-formed SFD must be passed across
the MII. While TSEC n _RX_DV is not asserted, TSEC n _RXD has no meaning.
In RGMII mode, data bits 3:0 are received on the rising edge of TSEC n _RX_CLK.
In RTBI mode, TSEC n _RXD[3:0] represents RCG[3:0] on the rising edge of TSEC n _RX_CLK
and RCG[8:5] are received on the falling edge of TSEC n _RX_CLK.
In TBI mode, TSEC n _RXD[3:0] represents RCG[3:0]. Together, with RCG[9:4], they represent the
10-bit encoded symbol of GMII receive signals.
In RMII mode TSEC n _RXD[1:0] represents RXD[1:0], which is considered valid when
TSEC n _RX_DV (CRS_DV) is asserted, or invalid otherwise.In FIFO mode TSEC n _RXD[7:4] with
TSEC n _RXD[3:0] represent one complete octet of data to be received from the external FIFO
device.
Receive error
Transmit clock in. In MII mode, TSEC n _TX_CLK is a continuous clock (2.5 or 25 MHz) that
provides a timing reference for the TSEC n _TX_EN, TSEC n _TXD, and TSEC n _TX_ER signals.
In GMII mode, this signal provides the 2.5 or 25 MHz timing reference during 10Base-T and
100Base-T and comes from the PHY. In 1000Base-T this clock is not used and
TSEC n _GTX_CLK (125 MHz) becomes the timing reference. The TSEC n _GTX_CLK is
generated in the eTSEC and provided to the PHY and the MAC. The TSEC n _TX_CLK is
generated in the PHY and provided to the MAC.
In TBI mode, this signal is PMA receive clock 1 at 62.5 MHz, split phase with PMA_RX_CLK0,
and is supplied by the SerDes.
In RMII mode this signal is the reference clock shared between transmit and receive, and is
supplied by the PHY.
In FIFO mode the transmit clock is a continuous clock whose maximum is defined by a ratio of
4.2:1 (platform:TxClk) in GMII mode and a ratio of 3.2:1 (platform:TxClk) in encoded mode.
This signal is not used in the eTSEC RTBI or RGMII modes.
Meaning
State
Asserted/Negated—In GMII, MII, or RMII mode, if TSEC n _RX_ER and
TSEC n _RX_DV are asserted, the PHY has detected an error in the current
frame.
In TBI mode, this signal represents RCG[9]. Together, with RCG[8:0], they
represent the 10-bit encoded symbol of GMII receive signals.
In FIFO mode, this signal represents either receive data error (GMII-style
protocols) or forms part of the receive control flags (encoded packet protocols).
This signal is not used in the RTBI or RGMII modes.
Description
Enhanced Three-Speed Ethernet Controllers
15-11