MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 63

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

16.2.3
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL
(high-speed current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be
used but may need to be AC-coupled due to the limited common mode input range allowed (100 to
400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock
driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to
AC-coupling.
Freescale Semiconductor
Interfacing With Other Differential Signaling Levels
SDn_REF_CLK
SDn_REF_CLK
Figure 45
fact that clock driver chip's internal structure, output impedance and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the MPC8533E SerDes reference clock receiver requirement
provided in this document.
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Figure 44. Single-Ended Reference Clock Input DC Requirements
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
through
Figure 48
are for conceptual reference only. Due to the
NOTE
High-Speed Serial Interfaces (HSSI)
0 V
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