MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 54

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

I
13.2
Table 47
54
All values refer to V
2
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Hold time (repeated) START condition (after this period,
the first clock pulse is generated)
Data setup time
Data hold time:
Data output delay time
Set-up time for STOP condition
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected
device (including hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. The MPC8533E provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
C
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
the undefined region of the falling edge of SCL.
B
= capacitance of one bus line in pF.
provides the AC timing parameters for the I
I
2
C AC Electrical Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
IH
I2DXKL
(min) and V
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter
has only to be met if the device does not stretch the LOW period (t
IL
CBUS compatible masters
(max) levels (see
I2SXKL
I2C
Table 47. I
symbolizes I
clock reference (K) going to the low (L) state or hold time. Also, t
I
2
C bus devices
Table
2
C AC Electrical Specifications
2
46).
C timing (I2) for the time that the data with respect to the start condition
Symbol
t
t
t
t
t
t
t
I2PVKH
I2KHDX
I2SVKH
I2DVKH
I2DXKL
I2OVKL
I2SXKL
t
t
t
t
V
V
f
I2CH
I2CR
I2CL
I2CF
2
I2C
NH
NL
C interfaces.
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
1
20 + 0.1 C
20 + 0.1 C
0.1 × OV
0.2 × OV
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
—
—
0
0
DD
DD
b
b
I2C
clock reference (K) going to the high
I2CL
IH
I2DVKH
min of the SCL signal) to bridge
Max
400
300
300
0.9
—
—
—
—
—
—
—
—
—
—
—
) of the SCL signal.
symbolizes I
Freescale Semiconductor
I2PVKH
Unit
kHz
μs
μs
μs
μs
ns
μs
μs
ns
ns
μs
V
V
symbolizes I
2
C timing (I2)
I2C
Notes
—
—
—
—
—
—
—
—
—
—
clock
for
2
3
4
4
2
C