PCA9665PW,118 NXP Semiconductors, PCA9665PW,118 Datasheet - Page 14

• Manufacturer Part Number: PCA9665PW,118
• Description: IC CNTRLR PARALLEL/I2C 20TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9665PW,118

• Package / Case: 20-TSSOP
• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4070-2; 935279244118; PCA9665PW-T; PCA9665PW-T

NXP Semiconductors
PCA9665_3
Product data sheet
7.3.2.4 The Time-out register, I2CTO (indirect address 04h)
7.3.2.5 The Parallel Software Reset register, I2CPRESET (indirect address 05h)
I2CTO is an 8-bit read/write register. It is used to determine the maximum time that SCL is
allowed to be in a LOW logic state before the I
PCA9665 initiates a forced action on the I
When the I
LOW SCL transition.
Table 21.
Table 22.
The Time-out register can be used in the following cases:
I2CPRESET is an 8-bit write-only register. Programming the I2CPRESET register allows
the user to reset the PCA9665 under software control. The software reset is achieved by
writing two consecutive bytes to this register. The first byte must be A5h while the second
byte must be 5Ah. The writes must be consecutive and the values must match A5h and
5Ah. If this sequence is not followed as described, the reset is aborted.
Bit
7
6:0
•
•
•
TE
When the bus controller, in the master mode, wants to send a START condition and
the SCL line is held LOW by some other device. Then the bus controller waits a time
period equivalent to the time-out value for the SCL to be released. In case it is not
released, the bus controller concludes that there is a bus error, loads 78h in the
I2CSTA register, generates an interrupt signal and releases the SCL and SDA lines.
After the microcontroller reads the status register, it needs to send a reset in order to
reset the bus controller.
In the master mode, the time-out feature starts every time the SCL goes LOW. If SCL
stays LOW for a time period equal to or greater than the time-out value, the bus
controller concludes there is a bus error and behaves in the manner described above.
When the I
every SCL transition. See
In case of a forced access to the I
access to the I
7
Symbol
TE
TO[6:0]
I2CTO - Time-out register (indirect register 04h) bit allocation
I2CTO - Time-out register (indirect register 04h) bit description
2
C-bus interface is operating, I2CTO is loaded in the time-out counter at every
TO6
2
6
C-bus interface is operating, I2CTO is loaded in the time-out counter at
2
C-bus”.)
Rev. 03 — 12 August 2008
Description
Time-out enable/disable
Time-out value. The time-out period = (I2CTO[6:0] + 1)
The time-out value may vary some, and is an approximate value.
TO5
5
TE = 1: Time-out function enabled
TE = 0: Time-out function disabled
Section 8.11 “Reset”
TO4
2
4
C-bus. (See more details in
2
C-bus.
2
C-bus state machine is reset or the
TO3
Fm+ parallel bus to I
3
for more information.
TO2
2
Section 8.9.3 “Forced
PCA9665
TO1
© NXP B.V. 2008. All rights reserved.
2
1
C-bus controller
143.36 s.
TO0
14 of 90
0