PCA9665PW,118 NXP Semiconductors, PCA9665PW,118 Datasheet - Page 77

• Manufacturer Part Number: PCA9665PW,118
• Description: IC CNTRLR PARALLEL/I2C 20TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9665PW,118

• Package / Case: 20-TSSOP
• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4070-2; 935279244118; PCA9665PW-T; PCA9665PW-T

NXP Semiconductors
Table 51.
All the timing limits are valid within the operating supply voltage and ambient temperature range; V
3.3 V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
PCA9665_3
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
t
t
C
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region SCL’s falling edge.
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
0.3 V; T
= minimum time for SDA data out to be valid following SCL LOW.
Parameter
SCL clock frequency
bus free time between a
STOP and START
condition
hold time (repeated)
START condition
set-up time for a
repeated START
condition
set-up time for STOP
condition
data hold time
data valid acknowledge
time
data valid time
data set-up time
LOW period of the SCL
clock
HIGH period of the SCL
clock
fall time of both SDA and
SCL signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by
the input filter
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
I
2
C-bus frequency and timing specifications
amb
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
= 40 C to +85 C; and refer to V
f
.
Conditions
Rev. 03 — 12 August 2008
[5][6]
IL
[1]
[2]
[3]
[7]
and V
Standard-mode
0.05
Min
250
4.7
4.0
4.7
4.0
4.7
4.0
50
0
0
-
-
-
IH
I
2
C-bus
with an input voltage of V
1000
Max
3.45
100
300
50
-
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast-mode I
Fm+ parallel bus to I
0.05
Min
100
1.3
0.6
0.6
0.6
1.3
0.6
50
0
0
-
b
b
[4]
[4]
SS
2
C-bus
to V
Max
400
300
300
0.9
50
-
-
-
-
-
-
-
-
-
IL
DD
of the SCL signal) in order to
DD
.
Fast-mode Plus
= 2.5 V
0.26
0.26
0.26
0.05
0.26
Min
0.5
0.5
50
50
PCA9665
0
0
-
-
-
© NXP B.V. 2008. All rights reserved.
2
I
2
C-bus controller
C-bus
1000
f
Max
0.45
0.2 V and
120
120
is specified at
50
-
-
-
-
-
-
-
-
-
77 of 90
Unit
kHz
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s