PCA9665PW,118 NXP Semiconductors, PCA9665PW,118 Datasheet - Page 48

• Manufacturer Part Number: PCA9665PW,118
• Description: IC CNTRLR PARALLEL/I2C 20TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9665PW,118

• Package / Case: 20-TSSOP
• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4070-2; 935279244118; PCA9665PW-T; PCA9665PW-T

NXP Semiconductors
PCA9665_3
Product data sheet
8.5.1 Buffered Master Transmitter mode of operation
8.5.2 Buffered Master Receiver mode of operation
8.5 Buffered mode examples
1. Program the I2CCOUNT register with the number of bytes that need to be sent to the
2. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in
3. Program I2CCON register to initiate the Master Transmitter Buffered sequence. In
4. After reading the I2CSTA status register, the I2CCON is programmed with STA = 0.
5. When the sequence has been executed, an Interrupt is asserted and the SI bit is set
6. More sequence (program I2CCOUNT register, load data bytes in I2CDAT buffer, write
1. Program the I2CCOUNT register with the number of bytes that need to be read from a
2. Load the I
I
and can be set to 0 or 1.
the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If
more than 68 bytes are written to the buffer, the data at address 00h will be
overwritten. The number of bytes that needs to be loaded in I2CDAT is equal to
BC[6:0] in the I2CCOUNT register. The number of data bytes sent is equal to BC[6:0],
therefore, if the number of data bytes loaded is greater than BC[6:0], the additional
data will not be sent. If the number of data bytes written to the buffer is less than
BC[6:0], the PCA9665 will still send out BC[6:0] data bytes.
Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and
the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA
register contains the status of the transmission. MODE bit must be set to ‘1’ each time
a write to the I2CCON register is performed.
That clears the previous Interrupt. If a START command has been previously sent, the
first byte loaded into the buffer and sent to the I
I
bytes that are sent to the I
in the I2CCON register. The I2CSTA register contains the status of the transmission
and the I2CCOUNT register contains the number of bytes that have been sent to the
I
the I2CCON register to send the data to the I
the sequence has been executed) can be performed as long as a STOP or Repeated
START command has not been sent. Master Transmitter Buffered mode ends when
the I2CCOUNT register is programmed with STO = 1.
slave device in the I
Receiver mode to let the PCA9665 know if the last byte received must be
acknowledged or not.
LB = 0: Last received byte is acknowledged and another sequence can be executed.
LB = 1: Last received byte is not acknowledged. The last sequence before sending a
STOP or Repeated START must be executed with LB = 1.
2
2
2
C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver mode only
C-bus address + R/W operation. In transmitter mode, R/W = 0 and the following
C-bus as described in
2
C-bus address + R/W = 1 in I2CDAT buffer.
Rev. 03 — 12 August 2008
2
C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used in
Table
2
C-bus are interpreted as data bytes.
42.
2
Fm+ parallel bus to I
C-bus, read the I2CSTA register when
2
C-bus is interpreted as the
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
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