PCA9665PW,118 NXP Semiconductors, PCA9665PW,118 Datasheet - Page 22

• Manufacturer Part Number: PCA9665PW,118
• Description: IC CNTRLR PARALLEL/I2C 20TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9665PW,118

• Package / Case: 20-TSSOP
• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4070-2; 935279244118; PCA9665PW-T; PCA9665PW-T

NXP Semiconductors
PCA9665_3
Product data sheet
8.3.2 Master Receiver Byte mode
In the Master Receiver Byte mode, a number of data bytes are received from a slave
transmitter one byte at a time (see
Transmitter Byte mode.
The Master Receiver Byte mode may now be entered by setting the STA bit. The I
state machine will first test the I
bus becomes free. When a START condition is transmitted, the Serial Interrupt flag (SI) is
set, the Interrupt line (INT) goes LOW and the status code in the status register (I2CSTA)
will be 08h. This status code must be used to vector to an interrupt service routine that
loads I2CDAT with the slave address and the data direction bit (SLA+R). A write to
I2CCON resets the SI bit, clears the Interrupt (INT goes HIGH) and allows the serial
transfer to continue.
When the slave address and the data direction bit have been transmitted, the serial
interrupt flag (SI) is set again, the Interrupt line (INT) goes LOW again and I2CSTA is
loaded with the following possible codes:
The appropriate action to be taken for each of these status codes is detailed in
ENSIO is not affected by the serial transfer and is not referred to in
After a repeated START condition (state 10h), the PCA9665 may switch to the Master
Transmitter mode by loading I2CDAT with SLA+W.
Remark: A master should not transmit its own slave address.
•
•
•
•
•
•
40h if an acknowledgment bit (ACK) has been received for the slave address with
direction bit
48h if a no acknowledgment bit (NACK) has been received for the slave address with
direction bit
38h if the PCA9665 lost the arbitration
B0h if the PCA9665 lost the arbitration and is addressed as a slave transmitter (slave
mode enabled with AA = 1)
68h if the PCA9665 lost the arbitration and is addressed as a slave receiver (slave
mode enabled with AA = 1)
D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a
General Call sequence (slave mode enabled with AA = 1 and General Call address
enabled with GC = 1 in I2CADR register).
Rev. 03 — 12 August 2008
2
C-bus and generate a START condition as soon as the
Figure
8). The transfer is initialized as in the Master
Fm+ parallel bus to I
Table
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
28.
Table
2
C-bus
22 of 90
28.