PCA9665PW,118 NXP Semiconductors, PCA9665PW,118 Datasheet - Page 8

• Manufacturer Part Number: PCA9665PW,118
• Description: IC CNTRLR PARALLEL/I2C 20TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9665PW,118

• Package / Case: 20-TSSOP
• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4070-2; 935279244118; PCA9665PW-T; PCA9665PW-T

NXP Semiconductors
PCA9665_3
Product data sheet
7.3.1.1 The Status register, I2CSTA (A1 = 0, A0 = 0)
7.3.1.2 The Indirect Pointer register, INDPTR (A1 = 0, A0 = 0)
7.3.1.3 The I
7.3.1 Direct registers
I2CSTA is an 8-bit read-only register. The two least significant bits are always zero. The
six most significant bits contain the status code. There are 30 possible status codes.
When I2CSTA contains F8h, it indicates the idle state and therefore no serial interrupt is
requested. All other I2CSTA values correspond to defined states. When each of these
states is entered, a serial interrupt is requested (SI = 1 and INT asserted LOW).
Remark: Data in I2CSTA is valid only when a serial interrupt occurs (SI = 1 and INT
asserted LOW). Reading the register when SI = 0 and INT is HIGH may cause wrong
values to be read.
Table 5.
Table 6.
Table 7.
Table 8.
INDPTR is an 8-bit write-only register. It contains a pointer to a register in the indirect
address space (IP[2:0]). The value in the register will determine what indirect register will
be accessed when the INDIRECT register is read or written, as defined in
I2CDAT is an 8-bit read/write register. It contains a byte of serial data to be transmitted or
a byte which has just been received. In master mode, this includes the slave address that
the master wants to send out on the I
address in the SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU
can read from and write to this 8-bit register while the PCA9665 is not in the process of
shifting a byte. This occurs when PCA9665 is in a defined state and the serial interrupt
flag is set. Data in I2CDAT remains stable as long as SI is set. Whenever the PCA9665
generates an interrupt, the I2CDAT register contains the data byte that was just
transferred on the I
Bit
7:2
1:0
Bit
7:3
2:0
ST5
7
7
-
2
C-bus Data register, I2CDAT (A1 = 0, A0 = 1)
Symbol
ST[5:0]
-
Symbol
-
IP2 to IP0
I2CSTA - Status register (A1 = 0, A0 = 0) bit allocation
I2CSTA - Status register (A1 = 0, A0 = 0) bit description
INDPTR - Indirect Register Pointer (A1 = 0, A0 = 0) bit allocation
INDPTR - Indirect Pointer register (A1 = 0, A0 = 0) bit description
ST4
6
6
-
2
C-bus.
Rev. 03 — 12 August 2008
Description
status code corresponding to the different I
always at zero
Description
reserved; must be written with zeroes
address of the indirect register
ST3
5
5
-
ST2
2
C-bus, with the most significant bit of the slave
4
4
-
ST1
Fm+ parallel bus to I
3
3
-
ST0
IP2
2
2
2
C-bus states
PCA9665
© NXP B.V. 2008. All rights reserved.
IP1
2
1
0
1
C-bus controller
Table
4.
IP0
0
0
0
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