PCA9665PW,118 NXP Semiconductors, PCA9665PW,118 Datasheet - Page 89

• Manufacturer Part Number: PCA9665PW,118
• Description: IC CNTRLR PARALLEL/I2C 20TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9665PW,118

• Package / Case: 20-TSSOP
• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 100µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4070-2; 935279244118; PCA9665PW-T; PCA9665PW-T

NXP Semiconductors
23. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.3.1
7.3.1.1
7.3.1.2
7.3.1.3
7.3.1.4
7.3.1.5
7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
7.3.2.4
7.3.2.5
7.3.2.6
8
8.1
8.1.1
8.1.2
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.4.1
PCA9665_3
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 6
PCA9665 modes. . . . . . . . . . . . . . . . . . . . . . . . 16
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . 6
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Direct registers . . . . . . . . . . . . . . . . . . . . . . . . . 8
The Status register, I2CSTA (A1 = 0, A0 = 0) . . 8
The Indirect Pointer register, INDPTR (A1 = 0,
A0 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
The I
A0 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
The Control register, I2CCON (A1 = 1, A0 = 1) 9
The indirect data field access register,
INDIRECT (A1 = 1, A0 = 0) . . . . . . . . . . . . . . 11
Indirect registers . . . . . . . . . . . . . . . . . . . . . . . 12
The Byte Count register, I2CCOUNT
(indirect address 00h) . . . . . . . . . . . . . . . . . . . 12
The Own Address register, I2CADR
(indirect address 01h) . . . . . . . . . . . . . . . . . . . 12
The Clock Rate registers, I2CSCLL and
I2CSCLH (indirect addresses 02h and 03h) . . 13
The Time-out register, I2CTO (indirect
address 04h). . . . . . . . . . . . . . . . . . . . . . . . . . 14
The Parallel Software Reset register,
I2CPRESET (indirect address 05h) . . . . . . . . 14
The I
(indirect address 06h) . . . . . . . . . . . . . . . . . . . 15
Configuration modes. . . . . . . . . . . . . . . . . . . . 16
Byte mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Buffered mode . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating modes . . . . . . . . . . . . . . . . . . . . . . 16
Byte mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Master Transmitter Byte mode . . . . . . . . . . . . 17
Master Receiver Byte mode . . . . . . . . . . . . . . 22
Slave Receiver Byte mode . . . . . . . . . . . . . . . 25
Slave Transmitter Byte mode . . . . . . . . . . . . . 29
Buffered mode . . . . . . . . . . . . . . . . . . . . . . . . 31
Master Transmitter Buffered mode . . . . . . . . . 31
2
2
C-bus Data register, I2CDAT (A1 = 0,
C-bus mode register, I2CMODE
Rev. 03 — 12 August 2008
8.4.2
8.4.3
8.4.4
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.6
8.7
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.9
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.10
8.11
8.12
8.13
9
9.1
9.1.1
9.2
9.3
10
10.1
10.2
10.3
10.4
Characteristics of the I
Application design-in information . . . . . . . . . 68
Master Receiver Buffered mode. . . . . . . . . . . 36
Slave Receiver Buffered mode. . . . . . . . . . . . 40
Slave Transmitter Buffered mode . . . . . . . . . . 45
Buffered mode examples . . . . . . . . . . . . . . . . 48
Buffered Master Transmitter mode of
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Buffered Master Receiver mode of
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Buffered Slave Transmitter mode . . . . . . . . . . 49
Buffered Slave Receiver mode. . . . . . . . . . . . 50
Example: Read 128 bytes in two 64-byte
sequences of an EEPROM
(I
and A1h for read operations) starting at
Location 08h. . . . . . . . . . . . . . . . . . . . . . . . . . 50
I2CCOUNT register . . . . . . . . . . . . . . . . . . . . 51
Acknowledge management (I
addresses and data) in Byte and Buffered
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Miscellaneous states . . . . . . . . . . . . . . . . . . . 57
I2CSTA = F8h. . . . . . . . . . . . . . . . . . . . . . . . . 57
I2CSTA = 00h . . . . . . . . . . . . . . . . . . . . . . . . . 57
I2CSTA = 70h . . . . . . . . . . . . . . . . . . . . . . . . . 57
I2CSTA = 78h . . . . . . . . . . . . . . . . . . . . . . . . . 58
Some special cases . . . . . . . . . . . . . . . . . . . . 58
Simultaneous repeated START conditions
from two masters . . . . . . . . . . . . . . . . . . . . . . 58
Data transfer after loss of arbitration . . . . . . . 58
Forced access to the I
I
SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 60
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
I
I
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
START and STOP conditions . . . . . . . . . . . . . 66
System configuration . . . . . . . . . . . . . . . . . . . 66
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 67
Specific applications. . . . . . . . . . . . . . . . . . . . 68
Add I
Add additional I
Convert 8 bits of parallel data into
I
2
2
2
2
2
C-bus obstructed by a LOW level on SCL or
C-bus timing diagrams, Unbuffered mode . . 62
C-bus timing diagrams, Buffered mode . . . . 64
C-bus serial data stream . . . . . . . . . . . . . . . 69
C-bus address = A0h for write operations
Fm+ parallel bus to I
2
C-bus port . . . . . . . . . . . . . . . . . . . . . . 68
2
C-bus ports . . . . . . . . . . . . . 69
2
2
C-bus . . . . . . . . . . . . . 58
C-bus . . . . . . . . . . . . 66
PCA9665
© NXP B.V. 2008. All rights reserved.
2
2
C-bus controller
C-bus
continued >>
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