PIC18F4520-I/P Microchip Technology Inc., PIC18F4520-I/P Datasheet - Page 114

• Manufacturer Part Number: PIC18F4520-I/P
• Description: 40 Pin, 32 KB Flash, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4520-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2420/2520/4420/4520
TABLE 10-5:
DS39631A-page 112
RC0/T1OSO/
T13CKI
RC1/T1OSI/CCP2
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Legend:
Note 1:
2:
Pin
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I
Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3.
Enhanced PWM output is available only on PIC18F4520 devices.
2
C/SMB = I
PORTC I/O SUMMARY
Function
CCP2
T1OSO
T13CKI
T1OSI
P1A
CCP1
SCK
SDA
SDO
RC0
RC1
RC2
RC3
SCL
RC4
RC5
RC6
RC7
SDI
TX
CK
RX
DT
2
C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
(2)
(1)
Setting
TRIS
0
1
x
1
0
1
x
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
2
C/SMB I
C/SMB I
Type
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATC<0> data output.
PORTC<0> data input.
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
Timer1/Timer3 counter input.
LATC<1> data output.
PORTC<1> data input.
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2 compare and PWM output; takes priority over port data.
CCP2 capture input.
LATC<2> data output.
PORTC<2> data input.
ECCP1 compare or PWM output; takes priority over port data.
ECCP1 capture input.
ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATC<3> data output.
PORTC<3> data input.
SPI™ clock output (MSSP module); takes priority over port data.
SPI clock input (MSSP module).
I
LATC<4> data output.
PORTC<4> data input.
SPI data input (MSSP module).
I
LATC<5> data output.
PORTC<5> data input.
SPI data output (MSSP module); takes priority over port data.
LATC<6> data output.
PORTC<6> data input.
Asynchronous serial transmit data output (USART module);
takes priority over port data. User must configure as output.
Synchronous serial clock output (USART module); takes priority
over port data.
Synchronous serial clock input (USART module).
LATC<7> data output.
PORTC<7> data input.
Asynchronous serial receive data input (USART module).
Synchronous serial data output (USART module); takes priority over
port data.
Synchronous serial data input (USART module). User must
configure as an input.
2
2
2
2
C™ clock output (MSSP module); takes priority over port data.
C clock input (MSSP module); input type depends on module setting.
C data output (MSSP module); takes priority over port data.
C data input (MSSP module); input type depends on module setting.
Description
 2004 Microchip Technology Inc.